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1. 发明专利

JP2011023085A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2011023085A
公开(公告)日：2011-02-03
申请号：JP2009169255
申请日：2009-07-17
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE TOSHIFUMI , ISHIGURO SHIGEFUMI , HAMANO TOMOYUKI , UEHARA KAZUTO
IPC分类号： G11C11/41
CPC分类号： G11C7/12 , G11C8/12 , G11C11/005
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which increases the speed of synchronization. SOLUTION: The semiconductor memory device has a BootRAM having a first number of banks, DataRAM having a second number of banks which is larger than the first number of banks, and an equalizing timer control circuit 42 that controls pre-charge operation performed for a bit line provided at the BootRAM and the DataRAM. When the BootRAM is synchronized with clock, the equalizing timer control circuit 42 changes an operation time for a second pre-charge operation different from that for a first pre-charge operation after receiving an address ADD, between completion of an initial first pre-charge operation and start of the next second pre-charge operation. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种增加同步速度的半导体存储器件。解决方案：半导体存储器件具有具有第一数量的存储体的BootRAM，DataRAM具有大于第一数量的存储体的第二数量的存储体;以及均衡定时器控制电路42，其控制执行的预充电操作对于BootRAM和DataRAM提供的位线。当BootRAM与时钟同步时，均衡定时器控制电路42在接收到地址ADD之后，在完成初始的第一预充电之后，改变与第一预充电操作不同的第二预充电操作的操作时间操作和开始下一个第二次预充电操作。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2008090941A Semiconductor memory device and its control method 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：JP2008090941A
公开(公告)日：2008-04-17
申请号：JP2006271145
申请日：2006-10-02
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： HAMANO TOMOYUKI , ISHIGURO SHIGEFUMI
IPC分类号： G11C11/4093 , G11C11/403
CPC分类号： G11C7/02 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C8/06 , G11C11/406 , G11C11/40615 , G11C11/4082 , G11C11/4093
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its control method, wherein noise tolerance can be improved while accelerating operation speed. SOLUTION: The device is provided with a memory cell array 10 provided with a plurality of memory cells MC holding data, an output buffer circuit 15 outputting data read out from the memory cell to the outside, and an input buffer circuit 16 receiving an address signal of the memory cell MC and having a noise filter 39 removing noise, wherein the filter length of the noise filter 39 is variable in accordance with output capability of the data in the output buffer circuit 15. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件及其控制方法，其中可以在加速操作速度的同时提高噪声容限。解决方案：该器件设置有存储单元阵列10，该存储单元阵列10具有保持数据的多个存储单元MC，输出缓冲器电路15，将从存储单元读出的数据输出到外部;以及输入缓冲电路16，存储单元MC的地址信号，并且具有去除噪声的噪声滤波器39，其中噪声滤波器39的滤波器长度根据输出缓冲电路15中的数据的输出能力而变化。版权所有（C））2008，JPO＆INPIT

3. 发明专利

JP2014186763A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2014186763A
公开(公告)日：2014-10-02
申请号：JP2013059144
申请日：2013-03-21
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMATA YOSHIHIKO , TABATA KOJI , HAMANO TOMOYUKI
IPC分类号： G11C16/06 , G11C16/02
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/24
摘要： PROBLEM TO BE SOLVED: To provide a sense amplifier capable of performing a write operation and simultaneously performing external transfer of a verification result.SOLUTION: A nonvolatile semiconductor memory device is provided with: a memory cell array that includes memory cells; and a sense amplifier that includes a latch unit (SDL) capable of holding write data and a detection unit (DTCT) and transfers either one of a first voltage (0 V) or a second voltage (VDDSA), which is higher than the first voltage, to a bit line according to the write data. The sense amplifier transfers either one of the first voltage or second voltage as a third voltage to the bit line according to a verification result and simultaneously transfers the third voltage to the detection unit.
摘要翻译：要解决的问题：提供一种能够执行写入操作并同时执行验证结果的外部传送的读出放大器。解决方案：非易失性半导体存储器件设置有：存储单元阵列，其包括存储单元; 以及包括能够保持写入数据的锁存单元（SDL）和检测单元（DTCT）的读出放大器，并且将第一电压（0V）或第二电压（VDDSA）中的任一个高于第一电压，根据写入数据到位线。感测放大器根据验证结果将第一电压或第二电压中的任一个作为第三电压转移到位线，并将第三电压同时传送到检测单元。

4. 发明专利

JP2013225363A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2013225363A
公开(公告)日：2013-10-31
申请号：JP2012097806
申请日：2012-04-23
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMATA YOSHIHIKO , TABATA KOJI , HAMANO TOMOYUKI
IPC分类号： G11C16/06 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device that can accelerate charging while suppressing an overshoot of a potential of a source node.SOLUTION: A semiconductor memory device comprises: an array 1 in which first and second blocks, where memory cells on a well are connected in series and which include NAND strings connected to sources, are disposed; a source line driver 7 that has a first node, CELSRC, connected to sources and charges/discharges potentials of the sources and the well; and voltage control circuits 61, 62 and 63 for controlling charging/discharge of the first node, CELSRC. The voltage control circuits 61, 62 and 63 comprise: boosters 62 and 63 that boost the potential of the well at the time of read-out operation and stop boosts of the sources and the well when detecting the potentials exceeding a first specified value; and pull-down driver 61 for controlling so as to discharge the potential of the first node, CELSRC, when the potentials of the sources exceed a second specified value.
摘要翻译：要解决的问题：提供一种半导体存储器件，其可以在抑制源极节点的电位的过冲的同时加速充电。解决方案：半导体存储器件包括：阵列1，其中第一和第二块，其中存储单元串联连接并且包括连接到源的NAND串，被布置; 源线路驱动器7，其具有连接到源极并且对源极和阱的电位进行充电/放电的第一节点CELSRC; 以及用于控制第一节点CELSRC的充电/放电的电压控制电路61,62和63。电压控制电路61,62和63包括：增强器62和63，其在读出操作时升高阱的电位，并且当检测到超过第一指定值的电位时停止源极和阱的升压; 和下拉驱动器61，用于控制，以便当源的电位超过第二指定值时，排出第一节点CELSRC的电位。

5. 发明专利

JP2012212485A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012212485A
公开(公告)日：2012-11-01
申请号：JP2011076440
申请日：2011-03-30
申请人： Toshiba Corp , 株式会社東芝
发明人： UEHARA KAZUTO , ISHIGURO SHIGEFUMI , HAMANO TOMOYUKI , SATO KAZUHIKO
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing erroneous determination of verify-operation.SOLUTION: A semiconductor device according to one embodiment comprises: an even number of memory cells connected to even-numbered word lines; an odd number of memory cells connected to odd-numbered word lines; an even number of control gate lines connected to the even-numbered word lines; an odd number of control gate lines connected to the odd-numbered word lines; a controller for alternately executing verify-operation with respect to the even number of memory cells and the odd number of memory cells. Further, a plurality of the even number of control gate lines is adjacent to one another and a plurality of the odd number of control gate lines is adjacent to one another. A first voltage is supplied to the even number of control gate lines and a second voltage is supplied to the odd number of control gate lines.
摘要翻译：要解决的问题：提供能够减少验证操作的错误确定的半导体器件。解决方案：根据一个实施例的半导体器件包括：偶数个连接到偶数字线的存储器单元; 与奇数字线连接的奇数个存储单元; 连接到偶数字线的偶数个控制栅极线; 连接到奇数字线的奇数控制栅极线; 控制器，用于相对于偶数个存储单元和奇数个存储单元交替执行验证操作。此外，多个偶数个控制栅极线彼此相邻，并且多个奇数个控制栅极线彼此相邻。第一电压被提供给偶数个控制栅极线，并且第二电压被提供给奇数个控制栅极线。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2013232264A Semiconductor memory device and reading method therefor 审中-公开
标题翻译：半导体存储器件及其读取方法
公开(公告)号：JP2013232264A
公开(公告)日：2013-11-14
申请号：JP2012104083
申请日：2012-04-27
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMATA YOSHIHIKO , SAKO MARIO , TABATA KOJI , HAMANO TOMOYUKI
IPC分类号： G11C16/06 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which reduces read errors of data.SOLUTION: The semiconductor memory device includes: a first transistor 24 to which a voltage VHSA (which is first voltage VDD) is supplied and which can supply first current to a bit line; a detection section SEN which detects the current passing through the bit line and reads held data in a memory cell connected to the bit line; and a second transistor 30 which can transfer any one of the first voltage VDD and a second voltage VX2SA larger than the first voltage, to the detection section. The second transistor charges the detection section SEN to any one of the first voltage VDD and the second voltage VX2SA while passing the first current to the bit line.
摘要翻译：要解决的问题：提供减少数据读取误差的半导体存储器件。解决方案：半导体存储器件包括：提供电压VHSA（其为第一电压VDD）的第一晶体管24，并且可以提供第一电流到一点点检测部分SEN，其检测通过位线的电流，并且读取与位线连接的存储单元中的保持数据; 以及能够将大于第一电压的第一电压VDD和第二电压VX2SA中的任一个传送到检测部的第二晶体管30。第二晶体管将检测部分SEN充电到第一电压VDD和第二电压VX2SA中的任何一个，同时将第一电流传送到位线。

7. 发明专利

JP2013225365A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2013225365A
公开(公告)日：2013-10-31
申请号：JP2012097925
申请日：2012-04-23
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMATA YOSHIHIKO , YOKOTA HIROKO , TABATA KOJI , HAMANO TOMOYUKI
IPC分类号： G11C16/06 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of reading data at a threshold level on a further negative side.SOLUTION: A semiconductor memory device comprises: a memory cell array in which memory cells capable of storing data are connected in series, strings having a source and drain are included, and each of the strings is connected in common through the source; each of the NAND strings; bit lines that are connected through corresponding drains; a sense amplifier (6) that includes a first transistor (BLX) and a second transistor (BLC) that are connected in series to each other and charge the bit lines to a first voltage (Vblc) when reading data from the memory cells; and a voltage generation circuit that supplies the sum of the first voltage and a second voltage to the gates of the first and second transistors while supplying the second voltage (CELSRC=VDD-Vblc) to the sources.
摘要翻译：要解决的问题：提供能够在另一负侧读取阈值电平的数据的半导体存储器件。解决方案：半导体存储器件包括：存储单元阵列，其中能够存储数据的存储器单元串联连接，包括源极和漏极的串，并且每个串通过源共同连接; 每个NAND串; 通过相应的排水管连接的位线; 读出放大器（6），其包括在从存储器单元读取数据时彼此串联连接并将位线充电至第一电压（Vblc）的第一晶体管（BLX）和第二晶体管（BLC）以及电压产生电路，其将第一电压和第二电压的和提供给第一和第二晶体管的栅极，同时向源提供第二电压（CELSRC = VDD-Vblc）。

8. 发明专利

JP2013225364A Semiconductor memory device and operation method for the same 审中-公开
标题翻译：半导体存储器件及其操作方法
公开(公告)号：JP2013225364A
公开(公告)日：2013-10-31
申请号：JP2012097807
申请日：2012-04-23
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMATA YOSHIHIKO , TABATA KOJI , KOGA MITSUHIRO , HAMANO TOMOYUKI , YOKOTA HIROKO
IPC分类号： G11C16/06 , G11C16/02
CPC分类号： G11C29/04 , G06F11/1008 , G11C16/0483 , G11C16/26 , G11C29/42
摘要： PROBLEM TO BE SOLVED: To provide a sense amplifier that enables a high-speed XOR operation while maintaining a size of a circuit area.SOLUTION: A semiconductor memory device comprises: a memory cell array 10 including strings in which memory cells capable of holding data are connected in series; a sense amplifier 12 that is provided with a first node SEN for detecting an amount of currents flowing through the memory cells and includes a first latch SDL and a second latch XDL for storing results detected by the first node SEN; a control section, sequencer 15, including a transfer control section that causes a first operation OR and a second operation NAND to be performed by using the data read-out from the memory cells and stored in the first latch SDL and the second latch XDL, subsequently causes a third operation AND to be performed by first results obtained by the first operation OR and second results obtained by the second operation NAND and determines whether or not erroneous reading-out with respect to the data read-out exists; and a detection section 12-3 for storing the third operation by the control section.
摘要翻译：要解决的问题：提供一种能够在保持电路面积的大小的同时进行高速异或运算的读出放大器。解决方案：半导体存储器件包括：存储单元阵列10，其包括能够保存数据的存储单元的串串联连接读出放大器12，其具有用于检测流过存储单元的电流量的第一节点SEN，并且包括第一锁存器SDL和第二锁存器XDL，用于存储由第一节点SEN检测到的结果; 控制部分，定序器15，包括通过使用从存储器单元读出并存储在第一锁存器SDL和第二锁存器XDL中的数据来执行第一操作OR和第二操作NAND的传送控制部分，随后通过第一操作OR获得的第一结果和通过第二操作NAND获得的第二结果执行第三操作AND并确定是否存在关于数据读出的错误读出; 以及用于存储控制部分的第三操作的检测部分12-3。

9. 发明专利

JP2011023084A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2011023084A
公开(公告)日：2011-02-03
申请号：JP2009169254
申请日：2009-07-17
申请人： Toshiba Corp , 株式会社東芝
发明人： HAMANO TOMOYUKI , ISHIGURO SHIGEFUMI , WATANABE TOSHIFUMI , UEHARA KAZUTO
IPC分类号： G11C11/41
CPC分类号： G11C8/04 , G11C11/41 , G11C2029/0411
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which attains high-frequency operation and high speed.
SOLUTION: The semiconductor memory device includes: an SRAM core 47 having a plurality of memory cells; an address counter 41a incrementing addresses including a row address and a column address in synchronization with clock, and outputting the incremented addresses sequentially; a counter address detecting circuit 42a detecting an address before the row address is switched in an address output from the address counter 41a and outputting the detected signal; and an equalization control circuit 46a performing pre-charge operation for a bit line connected to a memory cell in accordance with a detected signal output from the counter address detecting circuit 42a.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种实现高频操作和高速度的半导体存储器件。解决方案：半导体存储器件包括：具有多个存储单元的SRAM核心47; 地址计数器41a与时钟同步地增加包括行地址和列地址的地址，并顺序地输出递增地址; 计数器地址检测电路42a检测在从地址计数器41a输出的地址中切换行地址之前的地址并输出检测到的信号; 以及均衡控制电路46a，根据从计数器地址检测电路42a输出的检测信号，对连接到存储单元的位线执行预充电操作。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JPH05234367A 失效
公开(公告)号：JPH05234367A
公开(公告)日：1993-09-10
申请号：JP20925892
申请日：1992-08-05
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： OTO OSAMU , HAMANO TOMOYUKI , KOZUKA EIJI , MIYAWAKI NAOKAZU
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C29/00 , G11C29/24 , G11C29/42 , H01L27/10
摘要： PURPOSE:To reduce the size of a chip and to make the operation of the title memory device fast by a method wherein core planes which are provided with a row decoder and a column decoder which selectively activate a cell are provided inside a memory cell group and pieces of remaining data are allocated to the core planes. CONSTITUTION:Core planes n0 to n7 which are provided with row decoders 11, 12 and a column decoder 13 which selectively activate a cell in a desired manner are provided at the inside of memory cell groups 14, 15. Pieces of bit data for pieces of signal data are allocated to the core planes; in addition, pieces of bit data for pieces of remaining data are allocated. In the core plane n0, pieces of data at input/output parts IO1 to IO4 are read out/written by means of a column address signal, and pieces of data at input/output parts IO5 to IO8 are read out/written by means of a column address signal in the core plane n4. In addition, in the core plane n4, the readout/write operation of an input/ output part IO9 is performed by means of an address signal. Thereby, it is not required to provide a core plane which is exclusively used for the pieces of remaining data, the size of a chip can be reduced, and the operation of the title memory device can be made fast.

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