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1. 发明专利

JP2004103685A Semiconductor device and its fabricating process 审中-公开
标题翻译：半导体器件及其制造工艺
公开(公告)号：JP2004103685A
公开(公告)日：2004-04-02
申请号：JP2002260964
申请日：2002-09-06
申请人： Toshiba Corp , 株式会社東芝
发明人： TANABE YOSHIICHI , MORITSUKA KOHEI , KURIYAMA YASUHIKO , SUGIYAMA TORU , SUGIURA MASAYUKI
IPC分类号： H01L21/331 , H01L29/737
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, e.g. a heterojunction bipolar transistor, comprising a plurality of emitter layers formed on one base layer which is formed on a semiconductor substrate in which variation in heat dissipation can be suppressed significantly among emitters by dissipating heat efficiently, and to provide its fabricating process. SOLUTION: The semiconductor device comprises a base layer (23), a plurality of emitter layers (24, 24A and 24B) formed on the base layer, an insulating layer (60) having an opening including the plurality of emitter layers, and a wiring layer (70) provided to fill the opening wherein the plurality of emitter layers are connected, respectively, with the wiring layer. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供半导体器件，例如，一种异质结双极晶体管，包括形成在一个基底层上的多个发射极层，该多个发射极层形成在半导体衬底上，其中通过有效地耗散热量可以在发射器之间显着地抑制散热的变化，并提供其制造工艺。解决方案：半导体器件包括基底层（23），形成在基底层上的多个发射极层（24,24A和24B），具有包括多个发射极层的开口的绝缘层（60）以及设置成填充所述开口的布线层（70），其中所述多个发射极层分别与所述布线层连接。版权所有（C）2004，JPO

2. 发明专利

JP2004079886A Manufacturing method of packaging, semiconductor device and packaging 审中-公开
公开(公告)号：JP2004079886A
公开(公告)日：2004-03-11
申请号：JP2002240529
申请日：2002-08-21
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGIYAMA TORU , MORITSUKA KOHEI , SUGIURA MASAYUKI , KURIYAMA YASUHIKO , TANABE YOSHIICHI
IPC分类号： H01L23/12 , H01L23/00 , H01L23/485 , H01L23/488
CPC分类号： H01L24/05 , H01L21/78 , H01L23/488 , H01L23/564 , H01L23/66 , H01L24/03 , H01L24/06 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2223/6644 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/48624 , H01L2224/48644 , H01L2224/73265 , H01L2224/85444 , H01L2224/92247 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01031 , H01L2924/01047 , H01L2924/01067 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/05042 , H01L2924/10157 , H01L2924/10161 , H01L2924/10329 , H01L2924/1305 , H01L2924/1306 , H01L2924/13063 , H01L2924/13064 , H01L2924/14 , H01L2924/1423 , H01L2924/18301 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/01033 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method which reduces the ground inductance of a packaging. SOLUTION: The manufacturing method includes a step for forming a semiconductor device and a ground pad 11 for ground wiring of the semiconductor device in each of a plurality of semiconductor chip areas on a principal surface of a semiconductor wafer 1; a step for physically forming a separation groove 32 in a separation area for separating the plurality of semiconductor chip areas; a step for forming a ground metal layer 26 so as to be connected to the ground pad 11 of the semiconductor device in the separation groove 32; a step for polishing a rear surface of the semiconductor wafer until exposing the bottom of the separation groove, and separating the plurality of semiconductor chip areas in the separation groove 32 into independent semiconductor chips 21; a step for forming a conductive material on a ground provided on a front surface of a packaging board; and a step for packaging the semiconductor chips 21 on the conductive material so as to connect the metal layer 26 and the ground by the conductive material. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2005353796A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005353796A
公开(公告)日：2005-12-22
申请号：JP2004172185
申请日：2004-06-10
申请人： Toshiba Corp , 株式会社東芝
发明人： TANABE YOSHIICHI , SUGIYAMA TORU , KURIHARA NORIHIRO
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor device having a high bump-share strength and a manufacturing method for the semiconductor device. SOLUTION: A plurality of hetero-junction bipolar transistors 20 are formed on a GaAs semiconductor substrate 10 at specified intervals, and a first insulating film 30 is formed on these bipolar transistors 20. openings are formed to the first insulating film 30, and second insulating films 40 are formed so as to coat the first insulating film 30 with the exception of the openings. A feed metal 50 is formed on the second insulating films 40 and the openings. The structure of the feed metal 50 is composed of the three-layer structure as a lower layer, an intermediate layer, and an uppermost layer. An Au wiring 60 is formed on the uppermost layer of the feed metal 50. A passivation film 70 is formed at a desired place on the Au wiring 60, and an Au bump 80 is formed to the opening of the passivation film 70. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了获得具有高凸块共享强度的半导体器件和用于半导体器件的制造方法。解决方案：在GaAs半导体衬底10上以规定的间隔形成多个异质结双极晶体管20，在这些双极晶体管20上形成第一绝缘膜30.开口形成在第一绝缘膜30上，并且除了开口之外，形成第二绝缘膜40以涂覆第一绝缘膜30。馈电金属50形成在第二绝缘膜40和开口上。进料金属50的结构由作为下层，中间层和最上层的三层结构构成。 Au馈线60形成在馈电金属50的最上层。钝化膜70形成在Au布线60上的所需位置处，并且Au凸块80形成于钝化膜70的开口。
版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2004146557A Semiconductor element, semiconductor device and method for manufacturing them 审中-公开
标题翻译：半导体元件，半导体器件及其制造方法
公开(公告)号：JP2004146557A
公开(公告)日：2004-05-20
申请号：JP2002309257
申请日：2002-10-24
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGIYAMA TORU , MORITSUKA KOHEI , SUGIURA MASAYUKI , KURIYAMA YASUHIKO , TANABE YOSHIICHI
IPC分类号： H01L23/522 , H01L21/60 , H01L21/768
CPC分类号： H01L24/05 , H01L24/03 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/91 , H01L2224/04042 , H01L2224/24 , H01L2224/24051 , H01L2224/32225 , H01L2224/48 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73227 , H01L2224/92247 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01023 , H01L2924/01031 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/10329 , H01L2924/12041 , H01L2924/1305 , H01L2924/1306 , H01L2924/13063 , H01L2924/13064 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2224/05556 , H01L2924/3512 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device using a semiconductor element where dicing line width is reduced while ground inductance is suppressed and a wasteful region can be reduced on a wafer, and to provide a manufacturing method. SOLUTION: In the semiconductor element (200) provided with an upper face, sides and a backside, the sides have a vertical side face (220) which is formed almost vertically to the upper face and slant sides (210) projected toward the backside from the upper face in a forward taper shape, and wiring layers (240) to the backside from the upper face through the slant sides are disposed. Thus, the semiconductor element which can inexpensively be manufactured by increasing chip yield per wafer while ground inductance is suppressed with such constitution, the semiconductor device using the semiconductor element and the manufacturing method of them can be supplied. Consequently, a large industrial merit can be obtained. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种使用半导体元件的半导体器件，其中切割线宽度减小，而接地电感被抑制并且在晶片上可以减少浪费的区域，并且提供制造方法。解决方案：在具有上表面，侧面和背面的半导体元件（200）中，侧面具有垂直侧面（220），该垂直侧面（220）几乎垂直于上表面并且倾斜侧面（210）朝向设置从上表面向前锥形的背面，以及通过斜面从上表面到背面的布线层（240）。因此，通过以这种结构抑制接地电感，通过提高每个晶片的芯片产量，可以廉价地制造半导体元件，可以提供使用半导体元件的半导体器件及其制造方法。因此，可以获得大的工业优点。版权所有（C）2004，JPO

5. 发明专利

JP2005353815A Semiconductor device, its manufacturing method and defect detecting method thereof 有权
标题翻译：半导体器件及其制造方法及其缺陷检测方法
公开(公告)号：JP2005353815A
公开(公告)日：2005-12-22
申请号：JP2004172452
申请日：2004-06-10
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGIURA MASAYUKI , KURIYAMA YASUHIKO , SUGIYAMA TORU , TANABE YOSHIICHI , SHIBAMIYA MAKOTO
IPC分类号： H01L21/60 , H01L23/495 , H01L23/544
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a situation is avoided that a chip crack cannot be detected, and, even when micro-cracks occur in a compound semiconductor or the like, the chip crack can be detected. SOLUTION: In the semiconductor device, a pn junction 2 is formed in a band-shaped pattern so as to enclose an element region at a central portion in the peripheral portion of a semiconductor chip. A semiconductor pattern of one conductive type (n) is annularly formed to further have pads 3a, 3b connected electrically to the pattern. The semiconductor pattern 6 of the other conductive type (p) has a structure which has one end connected electrically to another pad. By measuring electric characteristics of the two pads, crazing and chipping occurred in the chip are detected at a good sensitivity. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了提供避免无法检测到芯片裂纹的情况的半导体器件，并且即使在化合物半导体等中发生微裂纹，也可以检测出芯片裂纹。解决方案：在半导体器件中，pn结2形成为带状图案，以便在半导体芯片的周边部分的中心部分处包围元件区域。一个导电类型（n）的半导体图案被环形地形成，以进一步具有与图案电连接的焊盘3a，3b。另一种导电类型（p）的半导体图形6具有一端与另一个焊盘电连接的结构。通过测量两个焊盘的电特性，以良好的灵敏度检测芯片中发生的裂纹和碎裂。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005311852A High frequency amplifying device 审中-公开
标题翻译：高频放大器件
公开(公告)号：JP2005311852A
公开(公告)日：2005-11-04
申请号：JP2004128154
申请日：2004-04-23
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGIURA MASAYUKI , KURIYAMA YASUHIKO , SUGIYAMA TORU , TANABE YOSHIICHI , SHIBAMIYA MAKOTO
IPC分类号： H03F3/60 , H01L23/498 , H01L23/50 , H01L23/522 , H01L23/66 , H01L29/00 , H03F3/19
CPC分类号： H01L23/66 , H01L23/49838 , H01L23/50 , H01L23/5223 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2223/6644 , H01L2223/665 , H01L2224/0401 , H01L2224/05553 , H01L2224/05599 , H01L2224/0603 , H01L2224/16 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48599 , H01L2224/48799 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/1305 , H01L2924/15787 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/20758 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H03F3/601 , H01L2924/00 , H01L2924/00012 , H01L2924/00011
摘要： PROBLEM TO BE SOLVED: To realize cost reduction and miniaturization of a high frequency amplifying device without lowering its performance. SOLUTION: This high frequency amplifying device 1 comprises a high frequency amplifier 6 having an input terminal and an output terminal, a first capacitor 17, and a second capacitor 18. The first capacitor 17 has a first electrode and a second electrode, and a first insulating film formed between the first electrode and the second electrode, and the first electrode is connected to the output terminal via a first inductor 14, and the second electrode is connected to a ground. The second capacitor 18 has a third electrode and a fourth electrode made of the same material as those of the first and second electrodes, and a second insulating film formed between the third electrode and the fourth electrode, made of the same material and having a thickness approximately the same as the first insulating film, and the third electrode is connected to the first electrode. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在不降低其性能的情况下实现高频放大装置的成本降低和小型化。解决方案：该高频放大装置1包括具有输入端子和输出端子的高频放大器6，第一电容器17和第二电容器18.第一电容器17具有第一电极和第二电极，以及形成在第一电极和第二电极之间的第一绝缘膜，并且第一电极经由第一电感器14连接到输出端子，并且第二电极连接到地。第二电容器18具有由与第一和第二电极相同的材料制成的第三电极和第四电极，以及形成在第三电极和第四电极之间的第二绝缘膜，由相同的材料制成并具有厚度大致与第一绝缘膜相同，第三电极与第一电极连接。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2000012512A METHOD OF MACHINING SEMICONDUCTOR SUBSTRATE SURFACE 失效
公开(公告)号：JP2000012512A
公开(公告)日：2000-01-14
申请号：JP17897998
申请日：1998-06-25
申请人： TOSHIBA CORP
发明人： NITTA TOMOHIRO , TANABE YOSHIICHI , KITAURA YOSHIAKI
IPC分类号： C23F1/02 , H01L21/306 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To attain a sufficient selectivity or etching rate by selectively etching a part of a substrate which is not covered with a mask layer, using an etching liq. which contains a chelating agent. SOLUTION: A chelating agent which can be used in the semiconductor structure processing method is a compd. having a plurality of donor atoms coupled with metal ions to form a chelate compd., e.g. polyaminocarboxylic acid, its salt, polyamide compd., oxycarboxylic acid, its salt, condensed phosphoric acid, glyoxyme, etc., pref. polyaminocarboxylic acid and its salt, esp. pref. ethylenediaminetetraacetic acid, and a semiconductor substrate is etched with a chemical liq. contg. a chelating agent. As a result, it is possible to well satisfactorily selectively etch without sputtering out, perform a rapid etching work, and conduct a surface work at high precision and at high productivity.

8. 发明专利

JPH0794436A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0794436A
公开(公告)日：1995-04-07
申请号：JP23343293
申请日：1993-09-20
申请人： TOSHIBA CORP
发明人： ANASE SEIJI , TANABE YOSHIICHI , KITAURA YOSHIAKI , NISHIBORI KAZUYA
IPC分类号： H01L21/265 , H01L21/338 , H01L29/78 , H01L29/812
摘要： PURPOSE:To provide a semiconductor device manufacturing method which can contribute to the improvements of the performance and microminiaturization of semiconductor devices and by which a high-concentration n-type thin layer channel can be formed with high reproducibility by suppressing the diffusion of a p-type impurity implanted in the form of ions for forming a buried layer to the surface side of a substrate. CONSTITUTION:In a semiconductor device manufacturing method containing a process for forming a high-concentration n-type thin layer channel 4 and p-type buried layer 3 underlying the channel 4 in a GaAs substrate 1 by ion implantation, Mg ions are implanted into a deep part of the substrate 1 as a p-type impurity after Ar ions are implanted into the surface section of the substrate 1 under a channeling generating condition and Si ions are implanted into a shallow part of the substrate as an n-type impurity. After implanting the Mg and Si ions, the substrate 1 is heat-treated to activate the Mg and Si.

9. 发明专利

JPH09252085A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09252085A
公开(公告)日：1997-09-22
申请号：JP5940996
申请日：1996-03-15
申请人： TOSHIBA CORP
发明人： TANABE YOSHIICHI , FUJIWARA IKUO , NISHIBORI KAZUYA , KITAURA YOSHIAKI
IPC分类号： H01L27/04 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To obtain a capacitance element having as high capacitance as possible, by forming an oxide layer of tungsten on the surface of a lower electrode on a semiconductor substrate, forming a dielectric layer on the oxide layer, and forming an upper electrode on the dielectric layer. SOLUTION: A tungsten film 5 to become a lower electrode is formed on a silicon substrate 1 forming an insulating film thereon, and coated with resist to form a resist pattern. With the pattern used as a mask the film 5 is patterned. The pattern is removed, annealed, an oxide layer 7 is formed on the film 5, and a Pt 11 for an upper electrode is formed on an STO film 9 as a dielectric layer on the layer 7. Thus, a capacitance element having as high capacitance as possible can be obtained.

10. 发明专利

JPH08274256A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08274256A
公开(公告)日：1996-10-18
申请号：JP247596
申请日：1996-01-10
申请人： TOSHIBA CORP
发明人： NISHIBORI KAZUYA , AOYAMA TOMONORI , KITAURA YOSHIAKI , TANABE YOSHIICHI , SUGURO KYOICHI , ABE KAZUHIDE , KOMATSU SHUICHI , OKUWADA HISAMI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/06 , H01L27/095 , H01L29/92
摘要： PURPOSE: To prevent the deterioration in characteristics caused by the oxidization of a capacitor electrode in a capacitor using an oxide dielectric film. CONSTITUTION: A SiO2 film 12 and the first wiring layer 13 are provided on a GaAs substrate 11 in the above-mentioned order. A capacitor 10 is formed on the first wiring layer 13. The lower electrode 14 of the capacitor 10 has a multilayer structure consisting of a Ti layer/Mo layer/Pt layer in the order from the bottom side. The dielectric film 15 of the capacitor 10 consists of strontium titanate. The upper electrode 16a of the capacitor is multilayer constructed by a WNx layer 21 (120nm)/a W-layer 22 (300nm) in the order from lower side. The surface of the upper electrode 16a, which comes in contact with the dielectric film 15a, is prescribed by a tungsten nitride layer 21.

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