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    • 1. 发明专利
    • Semiconductor device, its manufacturing method and defect detecting method thereof
    • 半导体器件及其制造方法及其缺陷检测方法
    • JP2005353815A
    • 2005-12-22
    • JP2004172452
    • 2004-06-10
    • Toshiba Corp株式会社東芝
    • SUGIURA MASAYUKIKURIYAMA YASUHIKOSUGIYAMA TORUTANABE YOSHIICHISHIBAMIYA MAKOTO
    • H01L21/60H01L23/495H01L23/544
    • H01L22/34H01L2924/0002H01L2924/00
    • PROBLEM TO BE SOLVED: To provide a semiconductor device in which a situation is avoided that a chip crack cannot be detected, and, even when micro-cracks occur in a compound semiconductor or the like, the chip crack can be detected. SOLUTION: In the semiconductor device, a pn junction 2 is formed in a band-shaped pattern so as to enclose an element region at a central portion in the peripheral portion of a semiconductor chip. A semiconductor pattern of one conductive type (n) is annularly formed to further have pads 3a, 3b connected electrically to the pattern. The semiconductor pattern 6 of the other conductive type (p) has a structure which has one end connected electrically to another pad. By measuring electric characteristics of the two pads, crazing and chipping occurred in the chip are detected at a good sensitivity. COPYRIGHT: (C)2006,JPO&NCIPI
    • 解决的问题:为了提供避免无法检测到芯片裂纹的情况的半导体器件,并且即使在化合物半导体等中发生微裂纹,也可以检测出芯片裂纹。 解决方案:在半导体器件中,pn结2形成为带状图案,以便在半导体芯片的周边部分的中心部分处包围元件区域。 一个导电类型(n)的半导体图案被环形地形成,以进一步具有与图案电连接的焊盘3a,3b。 另一种导电类型(p)的半导体图形6具有一端与另一个焊盘电连接的结构。 通过测量两个焊盘的电特性,以良好的灵敏度检测芯片中发生的裂纹和碎裂。 版权所有(C)2006,JPO&NCIPI
    • 3. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2010147240A
    • 2010-07-01
    • JP2008322704
    • 2008-12-18
    • Toshiba Corp株式会社東芝
    • SHIBAMIYA MAKOTOHORIE MITSUO
    • H01L29/866H01L21/822H01L27/04H01L27/06
    • PROBLEM TO BE SOLVED: To provide a semiconductor device having a bidirectional diode structure capable of suppressing degradation of ESD resistance capacity and reducing capacitance.
      SOLUTION: The semiconductor device includes: an n-type common cathode region 13 located on a surface of a p-type semiconductor substrate 11; a p-type first anode region 16 located on a surface of the common cathode region 13 and having carrier concentration that is high relative to that of the semiconductor substrate 11, and high to an extent dominantly causing Zener breakdown; a p-type second anode region 17 located on a surface of the common cathode region 13 away from the first anode region 16 and having carrier concentration equivalent to that of the first anode region 16; a p-type third anode region 18 separate from the first anode region 16, in contact with the second anode region 17, located on a surface of the common cathode region 13, and having low carrier concentration relative to that of the second anode region 17; a p-type front-back conduction region 15 connecting the semiconductor substrate 11 to the first anode region 16 and located in the common cathode region 13; a surface electrode 25 located on the second and third anode regions 17, 18; and a back electrode 26 on the back of the semiconductor substrate 11.
      COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:提供一种具有能够抑制ESD电阻降低和减小电容的双向二极管结构的半导体器件。 解决方案:半导体器件包括:位于p型半导体衬底11的表面上的n型公共阴极区域13; p型第一阳极区域16,其位于公共阴极区域13的表面上,并具有相对于半导体衬底11的载流子浓度高,并且主要地导致齐纳击穿的程度高; 位于公共阴极区域13的远离第一阳极区域16并且具有与第一阳极区域16相同的载流子浓度的p型第二阳极区域17; 与位于公共阴极区域13的表面上的与第二阳极区域17接触的第一阳极区域16的p型第三阳极区域18相对于第二阳极区域17的载流子浓度低 ; 将半导体衬底11连接到第一阳极区域16并位于公共阴极区域13中的p型前后导电区域15; 位于第二阳极区域17和第三阳极区域18上的表面电极25; 以及在半导体衬底11的背面上的背面电极26.版权所有(C)2010,JPO&INPIT