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1. 发明专利

JP2006013614A Thin film piezoelectric resonator 审中-公开
标题翻译：薄膜压电谐振器
公开(公告)号：JP2006013614A
公开(公告)日：2006-01-12
申请号：JP2004183942
申请日：2004-06-22
申请人： Toshiba Corp , 株式会社東芝
发明人： YANASE NAOKO , YASUMOTO YASUAKI , OHARA RYOICHI , ITAYA KAZUHIKO , SANO KENYA , NISHIGAKI MICHIHIKO , NAGANO TOSHIHIKO , ABE KAZUHIDE , SUGIYAMA TORU , MORITSUKA KOHEI , KAWAKUBO TAKASHI
IPC分类号： H03H9/17 , H01L41/09 , H01L41/22 , H01L41/23 , H03H9/58
摘要： PROBLEM TO BE SOLVED: To provide a small-sized thin film piezoelectric resonator even when the device is packaged. SOLUTION: The thin film piezoelectric device is provided with: thin film piezoelectric resonance elements FR1 to FR9 including a lower electrode 6, a piezoelectric film 8, and an upper electrode 12 formed on a first substrate 2; a first through-hole provided to the first substrate beneath the thin film piezoelectric resonance elements so as to be penetrated through the first substrate and acting like a lower cavity 22 of the thin film piezoelectric resonance elements; and a metallic projection film 30 for covering the thin film piezoelectric resonance elements and provided so as to form an upper cavity 35 of the thin film piezoelectric resonance elements with its face opposed to the thin film piezoelectric resonance elements and the upper face of the thin film piezoelectric resonance elements. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：即使在器件被封装时，也提供小型薄膜压电谐振器。解决方案：薄膜压电装置设置有：薄膜压电谐振元件FR1至FR9，其包括形成在第一基板2上的下电极6，压电膜8和上电极12; 第一通孔，其设置在薄膜压电谐振元件下面的第一基板上，以穿过第一基板并像薄膜压电谐振元件的下腔22一样起作用。以及用于覆盖薄膜压电谐振元件并且设置成形成薄膜压电谐振元件的上腔35的金属投影膜30，其表面与薄膜压电谐振元件和薄膜的上表面相对压电谐振元件。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JPH11274167A Heterojunction bipolar transistor 失效
标题翻译：异相双极晶体管
公开(公告)号：JPH11274167A
公开(公告)日：1999-10-08
申请号：JP7160798
申请日：1998-03-20
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGIYAMA TORU , HONGO SADAHITO , KURIYAMA YASUHIKO , NOZU TETSUO , TSUDA KUNIO , MORITSUKA KOHEI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737
摘要： PROBLEM TO BE SOLVED: To suppress the drop in current amplification factor during current application caused by the recombination between electrons and holes, in a heterojunction bipolar transistor. SOLUTION: An n-type GaAs collector layer 11 and a p-type GaAs base layer 14 are formed on a GaAs substrate 11, and an n-type AlGaAs passivation layer 15 is formed on a base layer 14. Emitter contact layers 17 and 18 with sectional area smaller than that of the passivation layer 15 are formed on the passivation layer 15. A base electrode 16 is formed on the base layer 14 and on the flank of the passivation layer 15.
摘要翻译：要解决的问题：在异质结双极晶体管中，抑制由电子和空穴之间的复合导致的电流施加期间的电流放大因子的下降。解决方案：在GaAs衬底11上形成n型GaAs集电极层11和p型GaAs衬底层14，在基极层14上形成n型AlGaAs钝化层15.发射极接触层17和18 在钝化层15上形成具有小于钝化层15的截面面积的截面积。基底电极16形成在钝化层15的基底层14和侧面上。

3. 发明专利

JP2008198731A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008198731A
公开(公告)日：2008-08-28
申请号：JP2007030976
申请日：2007-02-09
申请人： Toshiba Corp , 株式会社東芝
发明人： YOSHIOKA HIROSHI , MORITSUKA KOHEI , FUJIMOTO HIDETOSHI , NODA TAKAO
IPC分类号： H01L27/095 , H01L21/338 , H01L21/822 , H01L21/8232 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/15 , H01L29/778 , H01L29/812 , H01L33/00
CPC分类号： H01L2224/48091 , H01L2224/48465 , H01L2224/49107 , H01L2924/12032 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of efficiently reducing the influence of current collapse of a field effect transistor.
SOLUTION: This semiconductor device 100 is provided with a field effect transistor (FET) 103 having a gate connected to a first terminal 101 receiving a gate voltage to be applied, one end (drain) connected to a second terminal 102 receiving a current to be applied, and the other end (source) connected to a ground; a light-emitting diode (LED) 105 having one end (anode) connected to a contact point 104 between the first terminal 101 and the FET 103, and the other end (cathode) connected to a ground; and a resistor 106 connected to the LED 105 in series between the contact point 104 and the ground. In the semiconductor device 100, the FET 103 and the LED 105 are disposed so that at least the FET 103 can be irradiated with a light emitted from the LED 105.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够有效地减小场效应晶体管的电流崩溃的影响的半导体器件。解决方案：该半导体器件100设置有场效应晶体管（FET）103，其具有连接到接收要施加的栅极电压的第一端子101的栅极，连接到第二端子102的一端（漏极）要施加的电流，另一端（源极）连接到地面; 具有连接到第一端子101和FET103之间的接触点104的一端（阳极）和连接到地的另一端（阴极）的发光二极管（LED）105; 以及电阻器106，其连接到LED 105，其串联在接触点104和接地之间。在半导体器件100中，FET 103和LED 105被设置为使得至少可以用从LED 105发射的光照射FET 103。（C）2008，JPO＆INPIT

4. 发明专利

JP2004146557A Semiconductor element, semiconductor device and method for manufacturing them 审中-公开
标题翻译：半导体元件，半导体器件及其制造方法
公开(公告)号：JP2004146557A
公开(公告)日：2004-05-20
申请号：JP2002309257
申请日：2002-10-24
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGIYAMA TORU , MORITSUKA KOHEI , SUGIURA MASAYUKI , KURIYAMA YASUHIKO , TANABE YOSHIICHI
IPC分类号： H01L23/522 , H01L21/60 , H01L21/768
CPC分类号： H01L24/05 , H01L24/03 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/91 , H01L2224/04042 , H01L2224/24 , H01L2224/24051 , H01L2224/32225 , H01L2224/48 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73227 , H01L2224/92247 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01023 , H01L2924/01031 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/10329 , H01L2924/12041 , H01L2924/1305 , H01L2924/1306 , H01L2924/13063 , H01L2924/13064 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2224/05556 , H01L2924/3512 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device using a semiconductor element where dicing line width is reduced while ground inductance is suppressed and a wasteful region can be reduced on a wafer, and to provide a manufacturing method. SOLUTION: In the semiconductor element (200) provided with an upper face, sides and a backside, the sides have a vertical side face (220) which is formed almost vertically to the upper face and slant sides (210) projected toward the backside from the upper face in a forward taper shape, and wiring layers (240) to the backside from the upper face through the slant sides are disposed. Thus, the semiconductor element which can inexpensively be manufactured by increasing chip yield per wafer while ground inductance is suppressed with such constitution, the semiconductor device using the semiconductor element and the manufacturing method of them can be supplied. Consequently, a large industrial merit can be obtained. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种使用半导体元件的半导体器件，其中切割线宽度减小，而接地电感被抑制并且在晶片上可以减少浪费的区域，并且提供制造方法。解决方案：在具有上表面，侧面和背面的半导体元件（200）中，侧面具有垂直侧面（220），该垂直侧面（220）几乎垂直于上表面并且倾斜侧面（210）朝向设置从上表面向前锥形的背面，以及通过斜面从上表面到背面的布线层（240）。因此，通过以这种结构抑制接地电感，通过提高每个晶片的芯片产量，可以廉价地制造半导体元件，可以提供使用半导体元件的半导体器件及其制造方法。因此，可以获得大的工业优点。版权所有（C）2004，JPO

5. 发明专利

JP2004022818A Double heterojunction bipolar transistor 审中-公开
公开(公告)号：JP2004022818A
公开(公告)日：2004-01-22
申请号：JP2002175916
申请日：2002-06-17
申请人： Toshiba Corp , 株式会社東芝
发明人： MORITSUKA KOHEI
IPC分类号： H01L21/331 , H01L29/737
摘要： PROBLEM TO BE SOLVED: To provide a double heterojunction bipolar transistor which is small in the transient build-up voltage of a collector current, wherein the power efficiency when it is used, for example, for a high-frequency power amplifier, can be improved.
SOLUTION: There are provided a first semiconductor layer (11), which is formed on a semiconductor substrate and contains a first conductivity-type impurity of high concentration as a sub-collector, a second semiconductor layer (12), which is formed on the first semiconductor layer, and contains a first conductivity-type impurity of low concentration as a collector, a third semiconductor layer (13) which is formed on the second semiconductor layer, a fourth semiconductor layer (14) which is formed on the third semiconductor layer, and contains a second conductivity-type impurity of high concentration as a base, and a fifth semiconductor layer (15) which is formed on the fourth semiconductor layer, contains the first conductivity-type impurity as an emitter, and has forbidden band width larger than that of the fourth semiconductor layer. The third semiconductor layer has forbidden band width larger than that of the fourth semiconductor layer and spontaneous polarization.
COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2003077930A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003077930A
公开(公告)日：2003-03-14
申请号：JP2001268871
申请日：2001-09-05
申请人： Toshiba Corp , 株式会社東芝
发明人： HONMA SOICHI , SUGIYAMA TORU , MORITSUKA KOHEI
IPC分类号： H01L21/331 , H01L21/3205 , H01L21/60 , H01L23/52 , H01L29/737
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device where heat dissipating characteristics can be improved without the occurrence of element breakdown and bump electrodes can be easily microfabricated, and to provide its manufacturing method. SOLUTION: In the semiconductor device 1, an emitter electrode 31 is arranged on an emitter region 26 of a heterojunction bipolar transistor 20 of a compound semiconductor element 2, and an emitter main electrode terminal 42A is connected to the emitter electrode 31 through an opening 41A of an interlayer dielectric 40. A film thickness of the emitter main electrode terminal 42A is thick in comparison with that of the emitter electrode 31. The interlayer dielectric 40 includes at least an organic film, and the film thickness of the interlayer dielectric 40 is equivalent to that of the emitter main electrode terminal 42A. An Au stud bump electrode 43A is arranged on the emitter main electrode terminal 42A.
摘要翻译：要解决的问题：提供一种半导体器件，其中可以提高散热特性，而不会发生元件击穿，并且凸块电极可以容易地微制造，并提供其制造方法。解决方案：在半导体器件1中，发射极31配置在化合物半导体元件2的异质结双极晶体管20的发射极区域26上，发射极主电极端子42A通过开口41A与发射电极31连接发射极主电极端子42A的膜厚与发射电极31的膜厚相比较厚。层间电介质40至少包含有机膜，并且层间电介质40的膜厚等于与发射极主电极端子42A的距离。在发射极主电极端子42A上配置Au凸块电极43A。

7. 发明专利

JPH11274168A Manufacture of heterojuction bipolar transistor 失效
标题翻译：异形双极晶体管的制造
公开(公告)号：JPH11274168A
公开(公告)日：1999-10-08
申请号：JP7230898
申请日：1998-03-20
申请人： Toshiba Corp , 株式会社東芝
发明人： NOZU TETSUO , HONGO SADAHITO , SUGIYAMA TORU , KURIYAMA YASUHIKO , TSUDA KUNIO , MORITSUKA KOHEI
IPC分类号： H01L29/73 , H01L21/26 , H01L21/331 , H01L29/205 , H01L29/737
摘要： PROBLEM TO BE SOLVED: To desorb the hydrogen within a base layer without deteriorating the surface form, in a heterojunction bipolar transistor.
SOLUTION: A WN film 18 and a W film 19, of 200 nm thickness are sequentially formed by sputtering method on a sample where a p-type base layer 14, an n-type emitter layer 15, and an n-type GaAs layer 16, and an n-type emitter contact layer 17 are sequentially stacked (b). Then, the heterojunction bipolar transistor substrate 10 formed is heat-treated at 675°C for five minutes in a nitrogen atmosphere. After the heat treatment, by the use of an SiO
2 film covering the emitter region as mask, W film 19/WN film 18 are removed by RIE method using CF
4 and O
2 gases to form an electrode (c).
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：在异质结双极晶体管中，在基层内解吸氢而不损害表面形式。解决方案：在p型基极层14，n型发射极层15和n型GaAs层16的样品上通过溅射法依次形成200nm厚的WN膜18和W膜19 ，并且依次层叠n型发射极接触层17（b）。然后，形成的异质结双极晶体管基板10在氮气气氛中在675℃下热处理5分钟。热处理后，通过使用覆盖发射极区域的SiO 2膜作为掩模，通过使用CF 4和O 2气体的RIE法除去W膜19 / WN膜18以形成电极（c）。

8. 发明专利

JP2015029046A 半導体装置有权
标题翻译：半导体器件
公开(公告)号：JP2015029046A
公开(公告)日：2015-02-12
申请号：JP2014055668
申请日：2014-03-18
申请人：株式会社東芝 , Toshiba Corp
发明人： HORI YOICHI , NODA TAKAO , MORITSUKA KOHEI , OHARA RYOICHI
IPC分类号： H01L29/861 , H01L29/47 , H01L29/868 , H01L29/872
CPC分类号： H01L29/872 , H01L29/0603 , H01L29/0615 , H01L29/0619 , H01L29/0692 , H01L29/1608 , H01L29/66037 , H01L29/6606
摘要：【課題】サージ耐量の向上を図ることができる半導体装置を提供すること。【解決手段】第1導電形の第1半導体領域と、前記第1半導体領域とショットキー接合した第1電極と、前記第1半導体領域と前記第1電極との間に設けられた第2導電形の第2半導体領域と、前記第1半導体領域と前記第1電極との間に設けられ前記第1電極とオーミック接合した第2導電形の第3半導体領域と、前記第1半導体領域と前記第3半導体領域との間に設けられ前記第1半導体領域の不純物の濃度よりも高い不純物の濃度を有する第1導電形の第4半導体領域と、前記第3半導体領域と前記第1電極の間に設けられ前記第3半導体領域の不純物の濃度よりも高い不純物の濃度を有する第2導電形の第5半導体領域と、前記第1半導体領域の前記第1電極とは反対側に設けられた第2電極と、を備えた半導体装置。【選択図】図1
摘要翻译：要解决的问题：提供一种能够提高耐冲击性的半导体器件。解决方案：一种半导体器件包括：第一导电型第一半导体区域; 与所述第一半导体区域肖特基耦合的第一电极; 设置在第一半导体区域和第一电极之间的第二导电型第二半导体区域; 第二导电类型的第三半导体区域，设置在第一半导体区域和第一电极之间并且与第一电极欧姆耦合; 设置在所述第一半导体区域和所述第三半导体区域之间并且具有比所述第一半导体区域的杂质浓度高的杂质浓度的第一导电型第四半导体区域; 设置在所述第三半导体区域和所述第一电极之间并且具有比所述第三半导体区域的杂质浓度高的杂质浓度的第二导电型第五半导体区域; 以及设置在与设置有第一电极的一侧相对的第一半导体区域侧的第二电极。

9. 发明专利

JP2014063806A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2014063806A
公开(公告)日：2014-04-10
申请号：JP2012206800
申请日：2012-09-20
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKIYAMA YOKO , MORITSUKA KOHEI
IPC分类号： H01L25/18 , H01L23/00 , H01L25/07
CPC分类号： H01L29/7394 , H01L23/552 , H01L24/48 , H01L25/072 , H01L27/1211 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2924/00014 , H01L2924/1203 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing EMI noise while reducing a wiring length.SOLUTION: A semiconductor device includes a material absorbing a high-frequency electromagnetic wave and is provided with a plurality of first flat plates having a tabular shape. Any of the first flat plates are disposed above first connection wiring and second connection wiring.
摘要翻译：要解决的问题：提供能够降低线路长度的同时降低EMI噪声的半导体器件。解决方案：半导体器件包括吸收高频电磁波的材料，并且设置有多个具有平板状的第一平板。任何第一平板都设置在第一连接布线和第二连接布线之上。

10. 发明专利

JP2013201190A Junction field-effect transistor and method of manufacturing the same 审中-公开
标题翻译：连接场效应晶体管及其制造方法
公开(公告)号：JP2013201190A
公开(公告)日：2013-10-03
申请号：JP2012067426
申请日：2012-03-23
申请人： Toshiba Corp , 株式会社東芝
发明人： MORITSUKA KOHEI
IPC分类号： H01L21/337 , H01L21/338 , H01L27/098 , H01L29/808 , H01L29/812
CPC分类号： H01L29/66068 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/8083 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a junction field-effect transistor that improves a manufacturing margin of a threshold voltage and includes a reverse-conductive diode, and a manufacturing method of the junction field-effect transistor.SOLUTION: There is provided a junction field-effect transistor including a first-conductivity-type semiconductor substrate, a first-conductivity-type drift layer, a second-conductivity-type gate region, a first-conductivity-type channel layer, a first-conductivity-type source region, a source electrode, a drain electrode, a second-conductivity-type gate contact layer, and a gate electrode. The first-conductivity-type drift layer is provided on a first primary surface of the first-conductivity-type semiconductor substrate. The second-conductivity-type gate region is provided on a surface of the first-conductivity-type drift layer. The first-conductivity-type channel layer is provided on the first-conductivity-type drift layer and the second-conductivity-type gate region. The first-conductivity-type source region is provided on a surface of the first-conductivity-type channel layer so as to face the second-conductivity-type gate region.
摘要翻译：要解决的问题：提供提高阈值电压的制造裕度的结型场效应晶体管，并且包括反向导通二极管以及结型场效应晶体管的制造方法。解决方案：提供了一个结场包括第一导电型半导体衬底，第一导电型漂移层，第二导电型栅极区，第一导电型沟道层，第一导电型源极区，源电极，漏电极，第二导电型栅极接触层和栅电极。第一导电型漂移层设置在第一导电型半导体衬底的第一主表面上。第二导电型栅极区设置在第一导电型漂移层的表面上。第一导电型沟道层设置在第一导电型漂移层和第二导电型栅极区。第一导电型源极区域设置在第一导电型沟道层的表面上，以面向第二导电型栅极区域。

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