专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2008084517A Magnetic random access memory and resistance random access memory 有权
标题翻译：磁性随机访问存储器和电阻随机访问存储器
公开(公告)号：JP2008084517A
公开(公告)日：2008-04-10
申请号：JP2007206956
申请日：2007-08-08
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU ARITAKE
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L43/08
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/1673 , H01L27/24
摘要： PROBLEM TO BE SOLVED: To suppress read disturbance in a reference element in a magnetic random access memory performing spin injection writing.
SOLUTION: The magnetic random access memory is provided with a storage element 10-1 having a fixed layer (p) of which the magnetization direction is fixed, a recording layer (f) of which the magnetization direction is changed in accordance with a direction of a write current, and a non-magnetic layer held between the fixed layer and the recording layer, a first reference element 10-2 which has the fixed layer (p), the recording layer (f), and the non-magnetic layer held between the fixed layer and the recording layer and stores anti-parallel data, a second reference element 10-3 which has the fixed layer (p), the recording layer (f), and the non-magnetic layer held between the fixed layer and the recording layer and stores parallel data, and a current source CC2 applying a current to the first reference element 10-2 toward the recording layer from the fixed layer during read-out operation and applying a current to the second reference element 10-3 toward the fixed layer from the recording layer during read-out operation.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：抑制进行自旋注入写入的磁性随机存取存储器中的参考元件中的读取干扰。磁性随机存取存储器具有存储元件10-1，该存储元件10-1具有其固定的磁化方向的固定层（p），记录层（f）的磁化方向根据写入电流的方向和保持在固定层和记录层之间的非磁性层，具有固定层（p），记录层（f）和非磁性层的第一参考元件10-2，磁性层保持在固定层和记录层之间，并存储反并行数据，具有固定层（p）的第二参考元件10-3，记录层（f）和保持在固定层和记录层并且存储并行数据，以及电流源CC2，在电流读出操作期间从固定层向记录层施加电流到第一参考元件10-2，并向第二参考元件10施加电流 -3朝向固定层在读出操作期间。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2006099835A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2006099835A
公开(公告)日：2006-04-13
申请号：JP2004282030
申请日：2004-09-28
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU ARITAKE , TSUCHIDA KENJI , IWATA YOSHIHISA
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/10 , H01L27/105
CPC分类号： G11C11/16 , G11C7/062 , G11C7/14
摘要： PROBLEM TO BE SOLVED: To propose sequence for automatically setting the data value for a reference cell. SOLUTION: The semiconductor memory is equipped with a memory cell MTJ (M1), a pair of reference cells MTJ (D1), MTJ (D2) used for generating reference potential, a first read circuit 16 for determining the data of the memory cell MTJ (M1) by comparing read potential obtained from the memory cell MTJ (M1) with the reference potential, a second read circuit 17 for outputting a detecting signal Dout (ref), for indicating the state of a pair of the reference cells MTJ (D1), MTJ (D2) by detecting the state of the pair of the reference cells MTJ (D1), MTJ (D2), and a control circuit for controlling the writing to the pair of the reference cells MTJ (D1), MTJ (D2), based on the detecting signal Dout (ref). COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提出自动设置参考单元的数据值的顺序。解决方案：半导体存储器配备有用于产生参考电位的存储单元MTJ（M1），一对参考单元MTJ（D1），MTJ（D2），用于确定第一读取电路16的数据的第一读取电路16 通过将从存储单元MTJ（M1）获得的读取电位与参考电位进行比较的第二读取电路17，用于输出用于指示一对参考单元的状态的检测信号Dout（ref）的第二读取电路17，存储单元MTJ（M1）通过检测一对参考单元MTJ（D1），MTJ（D2）的状态以及用于控制对一对参考单元MTJ（D1）的写入的控制电路，MTJ（D1），MTJ（D2） MTJ（D2），基于检测信号Dout（ref）。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005276276A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2005276276A
公开(公告)日：2005-10-06
申请号：JP2004085577
申请日：2004-03-23
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU ARITAKE , TSUCHIDA KENJI
IPC分类号： G11C11/15 , G11C11/14 , G11C29/00 , G11C29/04 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C29/816 , G11C11/16 , G11C29/808
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which has a memory cell including a magneto-resistive effect element which can decrease the area of a writing current source occupying the whole chip. SOLUTION: The semiconductor integrated circuit device is provided with a main memory cell array 1, a redundancy memory cell array 3, a writing current source 17, a common node 13 which is connected to the writing current source 17, a first selector 9M which is connected between the common node 13 and the one end of a main writing wire 7M, and a second selector 9R which is connected between the common node 13 and the one end of a redundancy writing wire 7R. The redundancy memory cell array 3 is apart from the main memory cell array 1, and the main memory cell array 1 and the redundancy memory cell array 3 have the writing current source 17 in common via the common node 13. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种半导体集成电路器件，其具有包含磁阻效应元件的存储单元，该存储单元可以减小占用整个芯片的写入电流源的面积。解决方案：半导体集成电路器件设置有主存储单元阵列1，冗余存储单元阵列3，写入电流源17，连接到写入电流源17的公共节点13，第一选择器 9M，连接在公共节点13和主写字线7M的一端之间，第二选择器9R连接在公共节点13与冗余写入线7R的一端之间。冗余存储单元阵列3与主存储单元阵列1分开，并且主存储单元阵列1和冗余存储单元阵列3通过公共节点13具有共同的写入电流源17.版权：（ C）2006，JPO＆NCIPI

4. 发明专利

JP2004288311A Semiconductor storage device and control method therefor 审中-公开
公开(公告)号：JP2004288311A
公开(公告)日：2004-10-14
申请号：JP2003080587
申请日：2003-03-24
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAJIMA KENTARO , IWATA YOSHIHISA , SUNAI MASAYUKI , SHIMIZU ARITAKE
IPC分类号： G11C11/15 , G11C29/04 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C29/00
CPC分类号： G11C11/15
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of improving the reliability of write operations, and to provide a control method therefor. SOLUTION: The semiconductor storage device is provided with a plurality of word lines formed along a 1st direction, a plurality of bit lines formed along a 2nd direction perpendicular to the 1st direction, memory cells which are magnetic arranged at the intersections of the word lines and the bit lines and include magneto-resistive elements, row decoders for selecting a word line, column decoders for selecting a bit line, and a write circuit for supplying 1st and 2nd write currents, respectively, to the word line and the bit line selected by the row decoder and the column decoder, and writing data to the selected memory cells arranged at the intersections of the selected word line and the selected bit line, and the write circuit varies the 1st and 2nd write current values according to temperatures. COPYRIGHT: (C)2005,JPO&NCIPI

5. 发明专利

JP2013187594A Interface circuit 审中-公开
标题翻译：接口电路
公开(公告)号：JP2013187594A
公开(公告)日：2013-09-19
申请号：JP2012048889
申请日：2012-03-06
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU ARITAKE , KOYANAGI MASARU , SUEMATSU YASUHIRO
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509 , G11C7/1057 , G11C16/24 , G11C16/26 , H03K19/00361
摘要： PROBLEM TO BE SOLVED: To provide an interface circuit that reduces noise occurring in an output waveform.SOLUTION: A P side reset rate control section 5P changes a turnoff speed of a P channel field effect transistor PM on the basis of an intermediate voltage FPR, and an N side reset rate control section 5N changes a turnoff speed of an N channel field effect transistor NM on the basis of an intermediate voltage FNR.
摘要翻译：要解决的问题：提供一种降低输出波形中出现噪声的接口电路。解决方案：AP侧复位速率控制部分5P基于中间电压FPR改变P沟道场效应晶体管PM的截止速度，以及 N侧复位速率控制部5N基于中间电压FNR来改变N沟道场效应晶体管NM的截止速度。

6. 发明专利

JP2009003991A Semiconductor device and semiconductor memory test device 审中-公开
标题翻译：半导体器件和半导体存储器测试器件
公开(公告)号：JP2009003991A
公开(公告)日：2009-01-08
申请号：JP2007161558
申请日：2007-06-19
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU ARITAKE , MATSUO MIE , OSHIMA SHIGEO
IPC分类号： G11C29/12 , G01R31/28 , G11C16/02 , G11C16/06 , G11C29/56 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C5/145 , G11C5/04 , G11C5/066 , G11C5/143 , G11C16/30 , G11C29/12005 , G11C29/48 , G11C29/56 , G11C2029/5602 , H01L25/0657 , H01L25/18 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2924/01019 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which enables a test before the shipping of a memory chip by removing a pump circuit which supplies a voltage for operation from memory chips, and individually separating them as a pump chip to be mixedly packaged into an MCP (Multi Chip Package) chip. SOLUTION: The semiconductor device is provided with: a plurality of nonvolatile semiconductor memory devices; a booster circuit which generates a boosting voltage which operates the plurality of nonvolatile semiconductor memory devices; and a booster circuit controller which controls the generation operation of the boosting voltage in the booster circuit based on an operation sequence of the plurality of nonvolatile semiconductor memory devices. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其能够通过从存储芯片提供用于操作的电压的泵电路去除存储器芯片的运输之前进行测试，并且将它们单独地分离成作为混合的泵芯片封装成MCP（多芯片封装）芯片。解决方案：半导体器件设置有：多个非易失性半导体存储器件; 升压电路，其产生操作所述多个非易失性半导体存储器件的升压电压; 以及升压电路控制器，其基于多个非易失性半导体存储器件的操作顺序来控制升压电路中的升压电压的产生操作。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2007287193A Magnetic memory 有权
标题翻译：磁记忆
公开(公告)号：JP2007287193A
公开(公告)日：2007-11-01
申请号：JP2006109926
申请日：2006-04-12
申请人： Toshiba Corp , 株式会社東芝
发明人： UEDA YOSHIHIRO , INABA TSUNEO , SHIMIZU ARITAKE , ITAGAKI SEITARO
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C11/16
摘要： PROBLEM TO BE SOLVED: To provide a magnetic memory made suitable to a spin injection writing method.
SOLUTION: The magnetoresistive element 2 has first and second edges and is written with the first data by supplying current from the first edge to the second edge and is written with the second data by supplying current from the second edge to the first edge. A terminal of a first p-type MOSFET13 is connected to the first edge and an edge of a second p-type MOSFET14 is connected to the second edge. An edge of a first n-type MOSFET15 is connected to the first edge and an edge of a second n-type MOSFET16 is connected to the second edge. A first current source circuit 21 is connected to the other edges of the first and second p-type MOSFETs to supply current. A first current synch circuit 24 is connected to the other edges of the first and second n-type MOSFETs to take out current.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供适合于自旋注入写入方法的磁存储器。解决方案：磁阻元件2具有第一和第二边缘，并且通过从第一边缘向第二边缘提供电流来写入第一数据，并且通过从第二边缘向第一边缘提供电流来写入第二数据。第一p型MOSFET13的端子连接到第一边缘，并且第二p型MOSFET14的边缘连接到第二边缘。第一n型MOSFET15的边缘连接到第一边缘，并且第二n型MOSFET16的边缘连接到第二边缘。第一电流源电路21连接到第一和第二p型MOSFET的其它边缘以提供电流。第一电流同步电路24连接到第一和第二n型MOSFET的其它边缘以取出电流。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2014187162A Semiconductor device and method of trimming the same 审中-公开
标题翻译：半导体器件及其相互匹配的方法
公开(公告)号：JP2014187162A
公开(公告)日：2014-10-02
申请号：JP2013060655
申请日：2013-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： SUEMATSU YASUHIRO , KOYANAGI MASARU , INOUE SATOSHI , SHIMIZU ARITAKE
IPC分类号： H01L21/822 , G11C11/401 , G11C16/06 , H01L27/04 , H03K19/0175
CPC分类号： H03K19/017545
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that allows trimming terminal resistors and improving the characteristics of an ODT circuit, and to provide a method of trimming the same.SOLUTION: First, second, and third termination circuits 12, 13, and 14 are connected to an external connection terminal 11. At least the first termination circuit 12 includes first and second resistors R1 and R2 connected in parallel to the external connection terminal 11, a plurality of first-conductivity-type first transistors P1 to P4, and a plurality of second-conductivity-type second transistors N1 to N4. When the variation range of the first and second resistors R1 and R2 is within a first range, only the first termination circuit 12 is driven, and when the variation range of the first and second resistors is within a second range, the first and second termination circuits 12 and 13 are driven.
摘要翻译：要解决的问题：提供一种允许修整端子电阻器并改善ODT电路的特性并提供其修整方法的半导体器件。解决方案：第一，第二和第三终端电路12,13和14 至少第一终端电路12包括与外部连接端子11并联连接的第一和第二电阻器R1和R2，多个第一导电型第一晶体管P1至P4和多个第二导电型第二晶体管N1至N4。当第一和第二电阻器R1和R2的变化范围在第一范围内时，仅驱动第一终端电路12，并且当第一和第二电阻器的变化范围在第二范围内时，第一和第二终端电路12和13被驱动。

9. 发明专利

JP2013200933A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2013200933A
公开(公告)日：2013-10-03
申请号：JP2012070300
申请日：2012-03-26
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJIMURA TOMOFUMI , SHIMIZU ARITAKE
IPC分类号： G11C16/02 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To perform timing control of a signal during high-speed data transfer with more accuracy.SOLUTION: A semiconductor storage device 1 includes: a plurality of first output circuits 20 that respond to both of a riding edge and a trailing edge of a clock and each output a plurality of data signals DQ to the outside, and includes a plurality of first output pads 24; a second output circuit 21 that outputs a data strobe signal DQS in synchronization with the plurality of data signals DQ and includes a plurality of second output pads 25; a power source pad 22-1 that receives electric power for the plurality of first output circuits 20 from the outside; and a power source pad 22-2 that receives electric power for the second output circuit 21 from the outside. The second output circuit 21 includes a delay element 50 that adjusts timing of the data strobe signal DQS.
摘要翻译：要解决的问题：在高速数据传输期间以更高的精度执行信号的定时控制。解决方案：半导体存储设备1包括：多个第一输出电路20，其响应于骑行边缘和后缘并且每个将多个数据信号DQ输出到外部，并且包括多个第一输出焊盘24; 第二输出电路21，其与多个数据信号DQ同步地输出数据选通信号DQS，并且包括多个第二输出焊盘25; 从外部接收多个第一输出电路20的电力的电源焊盘22-1; 以及从外部接收第二输出电路21的电力的电源焊盘22-2。第二输出电路21包括调整数据选通信号DQS的定时的延迟元件50。

10. 发明专利

JP2011233842A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011233842A
公开(公告)日：2011-11-17
申请号：JP2010105624
申请日：2010-04-30
申请人： Toshiba Corp , 株式会社東芝
发明人： SUZUKI YOSHIHISA , SHIMIZU ARITAKE
IPC分类号： H01L27/10 , G11C16/04 , G11C16/06 , H01L21/822 , H01L21/8247 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/04 , H01L27/115 , H01L29/788 , H01L29/792 , H04B5/02
CPC分类号： G11C5/02 , G11C5/04 , G11C16/06 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/14 , H01L2924/30107 , H01L2924/3025 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device having a high speed interface capable of suppressing an increase of the number of wire bondings when the number of chips to be laminated is increased and further capable of suppressing an increase of chip areas caused by the formation of inductor elements.SOLUTION: The device includes: a NAND chip NC1 having an inductor element ID1 for exchanging a signal; a NAND chip NC0 having an inductor element ID0 for exchanging the signal; and a control chip CC0, in which a control circuit is formed for controlling operations of the NAND chips NC1, NC0 and an inductor element IDC is included for exchanging the signal between the inductor elements ID1, ID0. Outer peripheries of the inductor elements ID1, ID0 are included in a closed space of which the outer periphery of the inductor element IDC is extended in the direction perpendicular to a plane including the inductor element IDC, and the inductance of the inductor element IDC is larger than at least anyone of the inductance of the inductor elements ID1 or ID0.
摘要翻译：解决的问题：提供一种具有高速接口的非易失性半导体存储装置，能够抑制当层压芯片的数量增加时引线数的增加，并且还能够抑制芯片的增加由电感元件形成的区域。解决方案：该装置包括：具有用于交换信号的电感器元件ID1的NAND芯片NC1; 具有用于交换信号的电感元件ID0的NAND芯片NC0; 并且包括用于控制NAND芯片NC1，NC0和电感器元件IDC的操作的控制电路的控制芯片CC0，用于交换电感器元件ID1，ID0之间的信号。电感器元件ID1，ID0的外周包含在电感元件IDC的外周沿垂直于包括电感器元件IDC的平面的方向延伸的封闭空间中，并且电感器元件IDC的电感较大比电感元件ID1或ID0的电感中的至少任何一个。版权所有（C）2012，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式