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1. 发明专利

JP2012059830A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2012059830A
公开(公告)日：2012-03-22
申请号：JP2010200040
申请日：2010-09-07
申请人： Toshiba Corp , 株式会社東芝
发明人： OGIWARA TAKASHI , IWAI HITOSHI , ITAGAKI SEITARO
IPC分类号： H01L27/115 , G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
CPC分类号： G11C16/30 , H01L27/0688 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of preventing a writing error and a reading error while achieving further downscaling of the device.SOLUTION: A semiconductor memory device comprises a cell array constituted by memory cell strings, a plurality of voltage generation circuits disposed in a lower part of the cell array and a control circuit for controlling the voltage generation circuits, in which the plurality of memory cell strings each include: a semiconductor layer having a pair of columnar portions, and a connection portion formed so as to connect lower ends of the pair of columnar portions; a plurality of control gates perpendicular to the columnar portions; and a plurality of memory cell transistors formed in respective crossing portions between the columnar portions and the plurality of control gates, and during a writing operation and a reading operation, out of the plurality of voltage generation circuits, the control circuit does not allow the voltage generation circuit to be driven, which gives noise to the memory string to be written and read of the plurality of memory strings, and allows the voltage generation circuit to be driven, which does not give noise to the memory string to be written and read of the plurality of memory strings.
摘要翻译：要解决的问题：提供一种能够防止写入错误和读取错误同时实现器件的进一步缩小的半导体存储器件。解决方案：半导体存储器件包括由存储器单元串构成的单元阵列，设置在单元阵列的下部的多个电压产生电路和用于控制电压产生电路的控制电路，其中多个存储单元串各自包括：具有一对柱状部分的半导体层和形成为连接该一对柱状部分的下端的连接部分; 垂直于柱状部分的多个控制门; 以及形成在所述柱状部和所述多个控制栅极之间的交叉部分中的多个存储单元晶体管，并且在写入操作和读取操作期间，在所述多个电压产生电路中，所述控制电路不允许所述电压将要被驱动的发生电路给存储器串提供多个存储器串的写入和读取的噪声，并且允许驱动电压产生电路，这不会对要写入和读取的存储器串产生噪声多个存储器串。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2013004127A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2013004127A
公开(公告)日：2013-01-07
申请号：JP2011132424
申请日：2011-06-14
申请人： Toshiba Corp , 株式会社東芝
发明人： ITAGAKI SEITARO , YAMADA KUNIHIRO , IWATA YOSHIHISA
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C2213/71 , H01L27/11582 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of selectively performing erasing operation with respect to a specific memory string out of a plurality of memory strings.SOLUTION: A controlling circuit selectively erases data of a selected memory transistor in a selected memory string and inhibits erasing operation with respect to non-selected memory transistors in the selected memory string and non-selected memory strings. The controlling circuit brings a semiconductor layer of the selected memory string into a floating state and, subsequently, applies first voltages to non-selected word lines connected to gates of the non-selected memory transistors in the selected memory string and applies a second voltage smaller than the first voltages to selected word lines connected to a gate of the selected memory transistor in the selected memory string.
摘要翻译：要解决的问题：提供一种能够选择性地执行多个存储器串中的特定存储器串的擦除操作的非易失性半导体存储器件。解决方案：控制电路选择性地擦除所选择的存储器串中所选择的存储晶体管的数据，并且禁止相对于所选择的存储器串和未选择的存储器串中的未选择的存储器晶体管的擦除操作。控制电路使所选择的存储器串的半导体层进入浮置状态，并且随后对连接到所选存储器串中未选择的存储晶体管的栅极的未选择的字线施加第一电压，并施加较小的第二电压比对所选存储器串中选择的存储晶体管的栅极连接到所选字线的第一电压。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2011198435A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011198435A
公开(公告)日：2011-10-06
申请号：JP2010066938
申请日：2010-03-23
申请人： Toshiba Corp , 株式会社東芝
发明人： ITAGAKI SEITARO , FUKUZUMI YOSHIAKI , IWATA YOSHIHISA , KATSUMATA RYUTA
IPC分类号： G11C16/04 , G11C16/02 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/10 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device having selective transistors with excellent cut-off characteristics and low power consumption while reducing a manufacturing cost.SOLUTION: The nonvolatile semiconductor memory device has memory transistors MTr1 to MTr8, first and second drain side selective transistors SDTr1 and SDTr2, and first and second source side selective transistors SSTr1 and SSTr2. A control circuit AR2 applies a ground voltage GND to bit lines BL in increasing the threshold voltage of the first drain side selective transistor SDTr1, transfers the ground voltage GND to the body of the second drain side selective transistor SDTr2 by applying a reading voltage Vread to the gate of the second drain side selective transistor SDTr2 and thereby making the second drain side selective transistor SDTr2 conductive, and then accumulates the charge into a charge accumulation layer by applying a program voltage Vprg to the first drain side selective transistor SDTr1.
摘要翻译：要解决的问题：提供具有优异的截止特性和低功耗的选择性晶体管的非易失性半导体存储器件，同时降低制造成本。解决方案：非易失性半导体存储器件具有存储晶体管MTr1至MTr8，第一和第二漏极侧选择晶体管SDTr1和SDTr2，以及第一和第二源极侧选择晶体管SSTr1和SSTr2。控制电路AR2在增加第一漏极侧选择晶体管SDTr1的阈值电压时将接地电压GND施加到位线BL，通过施加读取电压Vread将接地电压GND传送到第二漏极侧选择晶体管SDTr2的主体第二漏极侧选择晶体管SDTr2的栅极，从而使第二漏极侧选择晶体管SDTr2导通，然后通过向第一漏极侧选择晶体管SDTr1施加编程电压Vprg将电荷累积到电荷累积层。

4. 发明专利

JP2011065723A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011065723A
公开(公告)日：2011-03-31
申请号：JP2009216403
申请日：2009-09-18
申请人： Toshiba Corp , 株式会社東芝
发明人： ITAGAKI SEITARO , FUKUZUMI YOSHIAKI , IWATA YOSHIHISA
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11578 , G11C16/26 , G11C16/32 , G11C16/3418 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device that prevents leakage current.
SOLUTION: A memory string MS includes memory transistors MTr1 to MTr8 connected in series. A control circuit AR2 reads data from the memory transistors MTr1 to 8. The memory string MS includes a U-shaped semiconductor layer 34 functioning as bodies of the memory transistors MTr1 to 8, a charge storage layer 33b formed to surround the U-shaped semiconductor layer 34 and configured to hold data by storing charges, and word line conductive layers 31a to 31d formed to surround the U-shaped semiconductor layer 34 via the charge storage layer 33b. In a reading operation, the control circuit AR2 applies a reading pulse voltage Vread to the gate of at least one of the memory transistors MTr1 to MTr8 of the unselected memory string MS, and applies ground potential Vss to the gate of another memory transistor MTr.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种防止泄漏电流的非易失性半导体存储器件。解决方案：存储器串MS包括串联连接的存储器晶体管MTr1至MTr8。控制电路AR2从存储晶体管MTr1至8读取数据。存储器串MS包括用作存储晶体管MTr1至8的主体的U形半导体层34，形成为围绕U形半导体的电荷存储层33b 层34并且被配置为通过存储电荷来保存数据，以及经由电荷存储层33b形成为围绕U形半导体层34的字线导电层31a至31d。在读取操作中，控制电路AR2将读取脉冲电压Vread施加到未选择存储器串MS的至少一个存储晶体管MTr1至MTr8的栅极，并将接地电位Vss施加到另一个存储晶体管MTr的栅极。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2012069205A Nonvolatile semiconductor memory 审中-公开
标题翻译：非易失性半导体存储器
公开(公告)号：JP2012069205A
公开(公告)日：2012-04-05
申请号：JP2010212861
申请日：2010-09-22
申请人： Toshiba Corp , 株式会社東芝
发明人： ITAGAKI SEITARO , KITO TAKASHI , OGIWARA TAKASHI , IWAI HITOSHI
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/30 , G11C16/344 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory that can selectively perform erasing operation.SOLUTION: A control circuit performs erasing operation on a selected cell unit in a selected memory block for discharging electric charge accumulated in a first memory transistor, and is not allowed to perform erasing operation on an unselected cell unit in the selected memory block. At the time of erasing, the control circuit increases voltage of a body of the first memory transistor included in the selected cell unit to a first voltage, sets voltage of a body of a first memory transistor included in the unselected cell unit at a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to gates of the first memory transistors included in the selected cell unit and the unselected cell unit.
摘要翻译：要解决的问题：提供可选择性地进行擦除操作的非易失性半导体存储器。解决方案：控制电路对所选择的存储器块中的选定单元单元执行擦除操作，用于对累积在第一存储晶体管中的电荷进行放电，并且不允许对选择的存储块中的未选择单元单元执行擦除操作。在擦除时，控制电路将包括在所选单元单元中的第一存储晶体管的主体的电压增加到第一电压，将未选择的单元单元中包括的第一存储晶体管的主体的电压设置为第二电压低于第一电压，并且将包括在所选择的单元单元和未选择单元单元中的第一存储晶体管的栅极施加等于或低于第二电压的第三电压。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2010199235A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2010199235A
公开(公告)日：2010-09-09
申请号：JP2009041157
申请日：2009-02-24
申请人： Toshiba Corp , 株式会社東芝
发明人： HISHIDA TOMOO , IWATA YOSHIHISA , ITAGAKI SEITARO , MAEDA TAKASHI
IPC分类号： H01L21/8247 , G11C16/02 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C8/08 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3454 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of performing erasing operation at a high speed. SOLUTION: A control circuit CC applies a voltage Vera1 to the other end of a selective drain side transistor s-SDTr and causes the selective drain transistor s-SDTr to go into an on-state and causes a memory transistor MTr3 on a drain side selective transistor SDTr side to go into on state, rather than a selective memory transistor s-MTr3; and applies a voltage Vera2, which is lower than the voltage Vera1 to a gate of the selective memory transistor s-MTr3. The potential difference between the voltage Vera1 and the voltage Vera2 is a potential difference, such that it pulls out electrons accumulated in the electric-charge accumulation layers of the memory transistors MTr1-MTr4. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够高速执行擦除操作的非易失性半导体存储器件。解决方案：控制电路CC将电压Vera1施加到选择性漏极侧晶体管s-SDTr的另一端，并使选择性漏极晶体管s-SDTr进入导通状态，并使存储晶体管MTr3在漏极侧选择晶体管SDTr侧进入导通状态，而不是选择存储晶体管s-MTr3; 并将低于电压Vera1的电压Vera2施加到选择存储晶体管s-MTr3的栅极。电压Vera1和电压Vera2之间的电位差是电位差，使得它拉出积累在存储晶体管MTr1-MTr4的电荷累积层中的电子。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2010161199A Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2010161199A
公开(公告)日：2010-07-22
申请号：JP2009002376
申请日：2009-01-08
申请人： Toshiba Corp , 株式会社東芝
发明人： ITAGAKI SEITARO , IWATA YOSHIHISA , KITO TAKASHI , KATSUMATA RYUTA , AOCHI HIDEAKI , NITAYAMA AKIHIRO , KITO MASARU , TANAKA HIROYASU , MAEDA TAKASHI , HISHIDA TOMOO
IPC分类号： H01L21/8247 , G11C16/02 , G11C16/04 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/30
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device capable of performing an erase operation with efficiency. SOLUTION: A non-volatile semiconductor memory device has: a memory string MS; a source side selection transistor SSTr having one end connected to one end of the memory string MS; a source line SL having one end connected to the other end of the source side selection transistor SSTr; a source side selection gate line SGS connected to a gate of the source side selection transistor SSTr; and a control circuit AR2 performing an erase operation for erasing data in memory cells. The control circuit AR2 is configured to boost the voltages of the source line SL and the source side selection gate line SGS in the erase operation, while keeping the voltage of the source line SL larger than the voltage of the source side selection gate line SGS by a predetermined potential difference. The predetermined potential difference is a potential difference Vth that causes a GIDL current. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够有效地执行擦除操作的非易失性半导体存储器件。解决方案：非易失性半导体存储器件具有：存储器串MS; 源极侧选择晶体管SSTr，其一端连接到存储器串MS的一端; 源极线SL，其一端连接到源极侧选择晶体管SSTr的另一端; 源极侧选择栅极线SGS，连接到源极侧选择晶体管SSTr的栅极; 以及执行用于擦除存储单元中的数据的擦除操作的控制电路AR2。控制电路AR2被配置为在擦除操作中升高源极线SL和源极侧选择栅极线SGS的电压，同时将源极线SL的电压保持为比源极侧选择栅极线SGS的电压大预定的电位差。预定电位差是导致GIDL电流的电位差Vth。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2013143160A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2013143160A
公开(公告)日：2013-07-22
申请号：JP2012002131
申请日：2012-01-10
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWAGUCHI KAZUAKI , KONO YOSHIHIRO , ITAGAKI SEITARO
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory which allows for accelerated data transmission.SOLUTION: A semiconductor memory is provided with: a first memory cell array 1 which includes a columnar semiconductor SC, and a memory string formed of a data holding memory cell including a charge storage layer and a control gate which are sequentially formed so as to cover the columnar semiconductor through a gate insulation film; a first bit line; a second bit line; a first data line S1 which is electrically connected to the first bit line and arranged adjacent to the memory cell array, having a first wiring length; a second data line S2 for transmission of the data which is electrically connected to the second bit line and arranged adjacent to the first data line, having a second wiring length larger than the first wiring length; and a segmented transmission circuit 33 which transmits the data alternately supplied from the first date line and the second data line at the timing corresponding to the difference between the first wiring length and the second wiring length.
摘要翻译：要解决的问题：提供一种允许加速数据传输的半导体存储器。解决方案：半导体存储器具有：包括柱状半导体SC的第一存储单元阵列1和由数据保持存储单元形成的存储器串包括依次形成为通过栅极绝缘膜覆盖柱状半导体的电荷存储层和控制栅极; 第一个位线第二位线第一数据线S1，其电连接到第一位线并且布置成与存储单元阵列相邻，具有第一布线长度; 用于传输与第二位线电连接并且布置成与第一数据线相邻的数据的第二数据线S2具有大于第一布线长度的第二布线长度; 以及分段发送电路33，其以对应于第一布线长度和第二布线长度之间的差的定时发送从第一日期行和第二数据线交替提供的数据。

9. 发明专利

JP2012252740A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2012252740A
公开(公告)日：2012-12-20
申请号：JP2011124127
申请日：2011-06-02
申请人： Toshiba Corp , 株式会社東芝
发明人： ITAGAKI SEITARO
IPC分类号： G11C16/02 , G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/32
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of selectively performing erase operation with respect to a specific memory string out of a plurality of memory strings.SOLUTION: A nonvolatile semiconductor memory device related to one embodiment includes: a memory cell array; a plurality of memory strings; a drain side selection transistor; a source side selection transistor; a plurality of word lines; a plurality of bit lines; a source line; a drain side selection gate line; a source side selection gate line; and a controlling circuit. The controlling circuit applies a first voltage to bit lines selected and performs erase operation with respect to memory strings connected to the bit lines selected, while applies a second voltage to bit lines not selected and prohibits the erase operation with respect to memory strings connected to the bit lines not selected.
摘要翻译：要解决的问题：提供一种能够选择性地对多个存储器串中的特定存储器串执行擦除操作的非易失性半导体存储器件。解决方案：一个实施例涉及的非易失性半导体存储器件包括：存储单元阵列; 多个存储器串; 漏极侧选择晶体管; 源极侧选择晶体管; 多个字线; 多个位线; 源线; 漏极侧选择栅线; 源极选择栅极线; 和控制电路。控制电路对所选择的位线施加第一电压，并对连接到所选择的位线的存储器串执行擦除操作，同时对未选择的位线施加第二电压，并且禁止对连接到所述存储器的存储器串的擦除操作未选择位线。版权所有（C）2013，JPO＆INPIT

10. 发明专利

JP2010080729A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2010080729A
公开(公告)日：2010-04-08
申请号：JP2008248350
申请日：2008-09-26
申请人： Toshiba Corp , 株式会社東芝
发明人： ITAGAKI SEITARO , IWATA YOSHIHISA , KITO TAKASHI , AOCHI HIDEAKI , KATSUMATA RYUTA , NITAYAMA AKIHIRO , KITO MASARU , TANAKA HIROYASU
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/1157 , G11C5/02 , G11C16/0483 , G11C16/08 , G11C16/30 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device of an NAND flash memory, which suppresses an increase in an occupied area. SOLUTION: Memory strings MS are arranged in m rows in a columnar direction for each memory block MB. Word line conductive layers 31a to 31d are laminated in n layers. A word connection layer 51 is arranged in the columnar direction and is formed in such a manner as to extend from one side to the vicinity of one end in the row direction of the word line conductive layers 31a to 31d. It is connected with the word line conductive layers 31a to 31d through a contact plug 511, and satisfies a relationship of (Formula 1):m≥n. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种NAND闪存的非易失性半导体存储器件，其抑制占用面积的增加。解决方案：对于每个存储器块MB，存储器串MS以柱状方向排列成m行。字线导电层31a至31d层压成n层。字连接层51沿圆柱方向排列，形成为从字线导电层31a〜31d的行方向的一端的一侧向附近形成。通过接触插头511与字线导电层31a〜31d连接，满足（式1）：m≥n的关系。版权所有（C）2010，JPO＆INPIT

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