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1. 发明专利

JP2012053980A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2012053980A
公开(公告)日：2012-03-15
申请号：JP2011272842
申请日：2011-12-13
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIBATA NOBORU , IMAMIYA KENICHI
IPC分类号： G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To solve the problem that it is difficult to increase writing speed because a distribution width of threshold voltage of each data needs to be narrowed.SOLUTION: A semiconductor memory includes: a semiconductor substrate; a memory cell array that is coupled to word lines and bit lines and in which a plurality of serially connected memory cells is placed in a matrix; a selection transistor for selecting the word lines; and a control circuit for controlling potential of the word lines and bit lines according to input data and controlling write, read and delete operations of data for the memory cells. The selection transistor is formed on a well of the semiconductor substrate. At the time of the write operation, a second negative voltage is input to the well and a third voltage (the third voltage≥the second negative voltage) is input to a predetermined unselected word line.
摘要翻译：要解决的问题：为了解决由于每个数据的阈值电压的分布宽度需要变窄而难以提高写入速度的问题。解决方案：半导体存储器包括：半导体衬底; 耦合到字线和位线并且其中多个串联的存储器单元被放置在矩阵中的存储单元阵列; 用于选择字线的选择晶体管; 以及控制电路，用于根据输入数据控制字线和位线的电位，并控制存储单元的数据的写入，读取和删除操作。选择晶体管形成在半导体衬底的阱上。在写入操作时，向阱输入第二负电压，并将第三电压（第三电压≥第二负电压）输入到预定的未选字线。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2009146499A Nonvolatile memory card 审中-公开
标题翻译：非挥发性记忆卡
公开(公告)号：JP2009146499A
公开(公告)日：2009-07-02
申请号：JP2007322361
申请日：2007-12-13
申请人： Toshiba Corp , 株式会社東芝
发明人： MURAKAMI TETSUYA , NARA NOBUYOSHI , IMAMIYA KENICHI
IPC分类号： G11C16/06 , G06K19/07 , G11C16/04
CPC分类号： G11C5/143
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory card in which a problem caused by detection errors between respective voltage detectors never be caused in the nonvolatile memory card and its controller, and circuit scale can be reduced. SOLUTION: The nonvolatile memory card 100A is provided with a nonvolatile memory 110A and its controller 120A, the nonvolatile memory 110A and the controller 120A are provided with a first logic section 111 and a second logic section 121 corresponding to them, the nonvolatile memory 110A is provided with a voltage detector 112b for detecting power source voltage supplied to the nonvolatile memory and the controller from the outside, and an output of the detection is supplied to the first logic section of the nonvolatile memory to which the voltage detector is provided, while it can be supplied to the second logic section of the controller or/and a logic section 111' of at least one added nonvolatile memory 110B through a buffer amplifier simultaneously. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种非易失性存储卡，其中在非易失性存储卡及其控制器中不会引起各个电压检测器之间的检测误差引起的问题，并且可以减小电路规模。解决方案：非易失性存储卡100A设有非易失性存储器110A及其控制器120A，非易失性存储器110A和控制器120A设置有与其对应的第一逻辑部分111和第二逻辑部分121，非易失性存储器存储器110A设置有用于检测从外部提供给非易失性存储器和控制器的电源电压的电压检测器112b，并且将检测的输出提供给提供有电压检测器的非易失性存储器的第一逻辑部分同时可以通过缓冲放大器将其提供给控制器的第二逻辑部分和/或至少一个相加的非易失性存储器110B的逻辑部分111'。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2007213806A Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：JP2007213806A
公开(公告)日：2007-08-23
申请号：JP2007096896
申请日：2007-04-02
申请人： Toshiba Corp , 株式会社東芝
发明人： HOSONO KOJI , NAKAMURA HIROSHI , TAKEUCHI TAKESHI , IMAMIYA KENICHI
IPC分类号： G11C16/06 , G11C16/02
摘要： PROBLEM TO BE SOLVED: To provide an EEPROM having a rewrite/read circuit for achieving a cache function and a multivalue logical operation function under optimal conditions. SOLUTION: A rewrite/read circuit 140 is provided with first and second latch circuits 1 and 2 selectively connected to a memory cell array and transferring data to each other. This circuit has a multivalue logical operation mode of storing 2-bit 4-value data as a range of different threshold value voltage in one memory cell, and rewriting/reading high and low order bits of the 4-value data by using the first latch circuits 1 and 2, and a cache operation mode of transferring data between the second latch circuit 2 and an input/output terminal for a second address during a period of data transfer between a memory cell selected by a first address and the first latch circuit 1. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有用于在最佳条件下实现高速缓存功能和多值逻辑运算功能的重写/读取电路的EEPROM。解决方案：重写/读取电路140具有选择性地连接到存储单元阵列并将数据彼此传送的第一和第二锁存电路1和2。该电路具有在一个存储单元中存储2位4值数据作为不同阈值电压的范围的多值逻辑运算模式，并且通过使用第一锁存器重写/读取4值数据的高位和低位电路1和2以及在由第一地址选择的存储单元与第一锁存电路1之间的数据传送期间在第二锁存电路2和第二地址的输入/输出端之间传送数据的高速缓存操作模式。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007184105A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2007184105A
公开(公告)日：2007-07-19
申请号：JP2007096898
申请日：2007-04-02
申请人： Toshiba Corp , 株式会社東芝
发明人： HOSONO KOJI , NAKAMURA HIROSHI , TAKEUCHI TAKESHI , IMAMIYA KENICHI
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide an EEPROM in which a cache function and a multi-level logic operation function can be achieved respectively with optimum conditions and which has a rewrite/read circuit. SOLUTION: The rewrite/read circuit 140 is connected selectively to a memory cell array, while has a first latch circuit 1 and a second latch circuit 2 in which data can be transferred each other, further, the circuit has a multi-level logic operation mode in which two bits quaternary data is stored in one memory cell as a range of different threshold voltage, high-order bits and low-order bits of quaternary data are rewritten/read using the first and the second latch circuits 1, 2, and a cache operation mode which transmits data between the second latch circuit 2 and an input/output terminal for the second address in a period in which data is transmitted between a memory cell selected by the first address and the first latch circuit 1 about one bit binary data stored in one memory cell. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种EEPROM，其中可以分别以最佳条件实现高速缓存功能和多级逻辑操作功能，并且具有重写/读取电路。解决方案：重写/读取电路140选择性地连接到存储单元阵列，同时具有第一锁存电路1和第二锁存电路2，其中数据可以彼此传输，此外，使用第一和第二锁存电路1重写/读取作为不同阈值电压的范围，四位数据的高位和低位的两位四进制数据存储在一个存储单元中的电平逻辑运算模式， 2，以及高速缓存操作模式，其在第一锁存电路1选择的存储单元与第一锁存电路1之间的数据传输的周期内，在第二锁存电路2和第二地址的输入/输出端之间发送数据，存储在一个存储单元中的一位二进制数据。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2007115406A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2007115406A
公开(公告)日：2007-05-10
申请号：JP2007024389
申请日：2007-02-02
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWAI KOICHI , IMAMIYA KENICHI , IKEHASHI TAMIO
IPC分类号： G11C29/12 , G11C16/02 , G11C16/04 , G11C16/06 , G11C29/42
摘要： PROBLEM TO BE SOLVED: To reduce test time when defect check of a bit line or a sense amplifier is performed in a wafer test of a NAND flash memory, and furthermore extremely reduce the test time through parallel processing of a plurality of chips. SOLUTION: In a wafer test of a NAND flash memory, when defect check of a bit line or a sense amplifier of a cell array in a memory chip is performed, output of an expectation register 42 holding expectation data being externally input is compared with output of latch circuits 41a, 41b, ..., 41n holding data read from the memory cell by a comparison circuit 43, and a result on whether they agree or not to each other is output. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了减少在NAND闪速存储器的晶片测试中执行位线或读出放大器的缺陷检查时的测试时间，并且还通过多个芯片的并行处理极大地减少了测试时间。解决方案：在NAND闪存的晶片测试中，当执行存储器芯片中的单元阵列的位线或读出放大器的缺陷检查时，保持外部输入的期望数据的期望寄存器42的输出是与通过比较电路43保持从存储单元读取的数据的锁存电路41a，41b，...，41n的输出相比较，并输出其是否彼此一致的结果。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006313925A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2006313925A
公开(公告)日：2006-11-16
申请号：JP2006175635
申请日：2006-06-26
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAMURA HIROSHI , ARITOME SEIICHI , IMAMIYA KENICHI , OHIRA HIDEKO , TAKEUCHI TAKESHI , SHIMIZU KAZUHIRO , NARITA KAZUHITO
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of preventing a failure caused by deterioration of etching accuracy in a region at a memory cell array end. SOLUTION: The semiconductor memory device includes first blocks 2-0, 2-N composed of first memory cell units to which a plurality of memory cells M 1 to M 8 are connected, and second blocks 2-1 to 2-(N-1) composed of second memory cell units to which a plurality of memory cells M 1 to M 8 are connected. A memory cell array 2 is constituted by disposing the first block at opposite ends and the second block at other portions. Constitution of the first memory cell unit on the side of the memory cell array end is different from that of the second memory cell unit. It is possible to prevent a failure caused by deterioration of etching accuracy of the region at the memory cell array end, and to realize high yield operation and high reliability operation substantially without causing an increase of a chip size. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够防止由存储单元阵列端的区域中的蚀刻精度劣化引起的故障的半导体存储器件。解决方案：半导体存储器件包括由第一存储单元单元组成的第一块2-0，2-N，多个存储单元M 1 至M SB 8 >与第二存储单元组合的第二块2-1至2-（N-1），多个存储单元M SB1至SBB < 被连接。存储单元阵列2通过将第一块布置在相对端部而将第二块布置在其它部分而构成。存储单元阵列端侧的第一存储单元单元的结构与第二存储单元单元的结构不同。可以防止由于存储单元阵列端的区域的蚀刻精度的劣化而导致的故障，并且实质上不会导致芯片尺寸的增加而实现高产量操作和高可靠性操作。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2006179175A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2006179175A
公开(公告)日：2006-07-06
申请号：JP2006022953
申请日：2006-01-31
申请人： Toshiba Corp , 株式会社東芝
发明人： KANDA KAZUE , IKEHASHI TAMIO , TAKEUCHI KEN , IMAMIYA KENICHI
IPC分类号： G11C29/12 , G01R31/28 , G11C16/02 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit where the output voltage state of an internal power circuit can be monitored simply by an external terminal and the trimming of internal voltage is easy. SOLUTION: The semiconductor integrated circuit 30 is basically provided with a comparing part 31 for comparing a prescribed voltage with a reference voltage, an internal voltage generation part 32 for generating the internal voltage based on an output from the comparing part 31, and a resistance division part 38 for dividing an internal voltage node 37 into the prescribed voltage by resistance division. In order to set an internal resistance value for having the prescribed voltage, the semiconductor integrated circuit 30 is provided with a test mode of supplying a desired trimming voltage from outside to the external terminal 35 connected to a first node 34 being a node of the internal voltage generation part 32 and the resistance division part 38, deactivating a feedback part 33 to the internal voltage generation part 32 by an output from the comparing part 31, and detecting a comparing result being the output from the comparing part 31 to decide the internal resistance value. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体集成电路，其中内部电力电路的输出电压状态可以通过外部端子简单地进行监视，并且内部电压的微调很容易。解决方案：半导体集成电路30基本上设置有用于将规定电压与参考电压进行比较的比较部分31，用于根据比较部分31的输出产生内部电压的内部电压产生部分32和电阻分割部38，用于通过电阻分割将内部电压节点37分割成规定的电压。为了设定具有规定电压的内部电阻值，半导体集成电路30具有从外部向连接到作为内部的节点的第一节点34的外部端子35提供期望的修整电压的测试模式电压产生部32和电阻分割部38，通过比较部31的输出使反馈部33停止到内部电压产生部32，并且检测比较结果作为比较部31的输出，以决定内部电阻值。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2006013538A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2006013538A
公开(公告)日：2006-01-12
申请号：JP2005229895
申请日：2005-08-08
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAMURA HIROSHI , OHIRA HIDEKO , IMAMIYA KENICHI , TAKEUCHI TAKESHI , ARITOME SEIICHI
IPC分类号： H01L21/8247 , H01L21/76 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent incorrect readout resulting from capacity coupling between wirings. SOLUTION: In blocks BLOCKi-1, BLOCKi, selective gate lines SG1 (149) are located, respectively. A contact section X1 to a selective gate line SG1 (149) in a block BLOCKi-1 is provided in a shunt region QQ. A selective gate bypass line 21i-1 is located in a block BLOCKi adjoining the block BLOCKi-1, although it connects with the selective gate line SG1 (149) in the block BLOCKi-1. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止由布线之间的电容耦合引起的错误读取。解决方案：在块BLOCKi-1，BLOCKi，分别位于选择栅极线SG1（149）。在分路区域QQ中设置有与块BLOCKi-1中的选择栅极线SG1（149）的接触部分X1。选择栅极旁路线21i-1位于与块BLOCKi-1相邻的块BLOCKi中，尽管它与块BLOCKi-1中的选择栅极线SG1（149）连接。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2005353275A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2005353275A
公开(公告)日：2005-12-22
申请号：JP2005247810
申请日：2005-08-29
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAMURA HIROSHI , IMAMIYA KENICHI , YAMAMURA TOSHIO , HOSONO KOJI , KAWAI KOICHI
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To shorten a required time for a whole write sequence by enabling input operation of write data in parallel with data write operation, in a NAND cell type EEPROM. SOLUTION: This circuit is provided with first operation and second operation in which a pass/fail result of its operation is held in a semiconductor chip after finish of operation, and the circuit has such operation that when the first operation and the second operation are performed continuously, both of the pass/fail result of the first operation and the pass/fail result of the second operation are outputted after finish of the first and the second operation. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过在NAND单元型EEPROM中通过使能与数据写入操作并行的写入数据的输入操作来缩短整个写入序列的所需时间。解决方案：该电路具有第一操作和第二操作，其中在操作完成之后其操作的通过/失败结果被保持在半导体芯片中，并且电路具有这样的操作，即当第一操作和第二操作在第一操作和第二操作完成之后，输出第一操作的通过/失败结果和第二操作的通过/失败结果。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2003030993A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2003030993A
公开(公告)日：2003-01-31
申请号：JP2001216980
申请日：2001-07-17
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWAI KOICHI , IMAMIYA KENICHI , NAKAMURA HIROSHI
IPC分类号： G11C16/02 , G06F12/00 , G06F12/04 , G11C11/34 , G11C16/04 , G11C16/06 , G11C16/10 , H01L27/115
CPC分类号： G11C16/105 , G11C7/1006 , G11C7/1021 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/102 , G11C16/3431 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To rewrite data of one part of data read of one page portion read from a memory cell array and to write the result in a different page. SOLUTION: Data read, from a memory cell MC of one page in one block BL of a memory cell array, are held in a data-holding circuit 12. The data- holding circuit 12 has a plurality of latch circuits 24; in these plurality of latch circuits 24, addresses are specified for the latch circuits 24 by a column address. Then data for rewriting is supplied to the latch circuits 24, in which an address is specified by a column address, and rewrite of data is conducted by holding data by the latch circuit 24. Data corresponding to one page, after data rewrite is written in a page, in the memory cell array corresponding to a page address (row address).
摘要翻译：要解决的问题：重写从存储单元阵列读取的一页部分读取的一部分数据，并将结果写入不同页面。解决方案：从存储单元阵列的一个块BL中的一页的存储单元MC读取的数据被保存在数据保持电路12中。数据保持电路12具有多个锁存电路24; 在这些多个锁存电路24中，通过列地址为锁存电路24指定地址。然后将用于重写的数据提供给锁存电路24，其中通过列地址指定地址，并且通过锁存电路24保持数据来进行数据的重写。数据重写之后对应于一页的数据被写入在与存储单元阵列对应的页面地址（行地址）中。

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