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1. 发明专利

JP2011192898A Semiconductor memory device, and method of manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2011192898A
公开(公告)日：2011-09-29
申请号：JP2010059236
申请日：2010-03-16
申请人： Toshiba Corp , 株式会社東芝
发明人： YONEHAMA KEISUKE , SHIMIZU KAZUHIRO
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce an influence of impurities in a channel region of a select transistor on a memory cell transistor by setting a threshold voltage of the select transistor to a predetermined value. SOLUTION: A semiconductor memory device includes memory cell transistors MC0 to MC15, and select transistors ST1 and ST2, wherein dummy cell transistors DC0 and DC1 which are not used as memory elements are provided between the select transistors and memory cell transistors. Gate electrodes 13 of the select transistors have a first conductive layer and a second conductive layer, which are electrically connected by connection parts 16. Impurity concentrations of channel regions of the select transistors are higher than those of channel regions of the memory cell transistors. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过将选择晶体管的阈值电压设定为预定值来减小选择晶体管的沟道区域中的杂质对存储单元晶体管的影响。解决方案：半导体存储器件包括存储单元晶体管MC0至MC15，以及选择晶体管ST1和ST2，其中不用作存储元件的虚设单元晶体管DC0和DC1设置在选择晶体管和存储单元晶体管之间。选择晶体管的栅电极13具有通过连接部分16电连接的第一导电层和第二导电层。选择晶体管的沟道区的杂质浓度高于存储单元晶体管的沟道区的杂质浓度。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2007300136A Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：JP2007300136A
公开(公告)日：2007-11-15
申请号：JP2007186274
申请日：2007-07-17
申请人： Toshiba Corp , 株式会社東芝
发明人： WATABE HIROSHI , YAEGASHI TOSHITAKE , ARITOME SEIICHI , SHIMIZU KAZUHIRO , TAKEUCHI YUJI
IPC分类号： H01L27/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce the resistance of a select gate electrode in a NAND cell unit.
SOLUTION: In a nonvolatile semiconductor memory, each of a first and a second select gate electrodes SGD has a plurality of contact regions regularly arranged in a row direction, lies adjacent to a column direction by holding the diffusion layer or the source diffusion layer of a NAND cell unit, and extending to a row direction. The contact region of the first gate electrode and the contact region of the second select gate electrode are arranged as they are not face to each other. An interconnect wire SDL formed upper layer than the first select gate electrode is connected in the region of the first select gate electrode. The interconnect wire SDL is disposed on a memory cell in the NAND cell unit in the first select gate electrode side.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：降低NAND单元单元中的选择栅电极的电阻。解决方案：在非易失性半导体存储器中，第一和第二选择栅电极SGD中的每一个具有沿行方向规则排列的多个接触区域，通过保持扩散层或源极扩散位于与列方向相邻的位置 NAND单元单元的层，并且延伸到行方向。第一栅电极的接触区域和第二选择栅电极的接触区域彼此不相对地布置。与第一选择栅电极相比形成的上层的互连线SDL连接在第一选择栅电极的区域中。互连线SDL设置在第一选择栅电极侧的NAND单元单元中的存储单元上。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2007081434A Non-volatile semiconductor storage device 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：JP2007081434A
公开(公告)日：2007-03-29
申请号：JP2006337208
申请日：2006-12-14
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU KAZUHIRO , ARITOME SEIICHI
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/786 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a fine flash memory with high integration, superior in element isolation capability, and with small parasitic resistors and capacitances. SOLUTION: A NAND type flash EEPROM is formed on SOI substrate. An element region (active layer) has a lattice pattern, and a groove between the lattice patterns is embedded by an insulator. Elements of row direction are perfectly separated by the insulator. A silicon thin film in which memory cell is formed contains a minute amount of n-type impurity, and is located near an intrinsic semiconductor. A silicon thin film which is formed with a peripheral circuit and a selective gate transistor is p-type. A diffusion layer of memory cell and the selective gate transistor is n-type. A channel of each memory cell which constitutes NAND strings is configured at least two regions where threshold values are different. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供高集成度，元件隔离能力优异以及小的寄生电阻和电容的精细闪存。解决方案：在SOI衬底上形成NAND型快闪EEPROM。元件区域（有源层）具有格子图案，栅格图案之间的沟槽被绝缘体嵌入。行方向的元素被绝缘体完全分离。其中形成存储单元的硅薄膜含有微量的n型杂质，并且位于本征半导体附近。形成有外围电路和选择栅极晶体管的硅薄膜是p型的。存储单元的扩散层和选择栅极晶体管是n型。构成NAND串的每个存储单元的通道配置有至少两个阈值不同的区域。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2011071332A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011071332A
公开(公告)日：2011-04-07
申请号：JP2009221281
申请日：2009-09-25
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU KAZUHIRO , HORII HIDEHITO
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42324 , H01L27/11521 , H01L29/4234 , H01L29/7881 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To achieve a cell configuration that ensures a dielectric strength of each memory cell in the case of microfabrication, and controls a minute threshold distribution.
SOLUTION: The nonvolatile semiconductor memory device includes a plurality of element isolation insulating films DI formed in a surface layer of a semiconductor substrate S, a plurality of element regions AA defined in the element isolation insulating films DI, a plurality of gate configurations including a charge storage layer FG formed on the semiconductor substrate S through a tunnel oxide film 10 and a control gate CG formed on the charge storage layer FG through a gate insulating film 20, respectively, a plurality of impurity diffusion layers IDL formed in the element regions AA so as to pinch the surface layer of the semiconductor substrate S beneath the gate configurations therebetween, an insulating film 60 formed with silicon oxide so as to bury between the gate configurations, and an insulating film 40 formed with silicon nitride so as to come into contact with a sidewall of the gate configuration. In the nonvolatile semiconductor memory device, the base of the gate insulating film 40 is separated from the surface of the semiconductor substrate S by at least a half or more of the height of the charge storage layer FG.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了实现在微细加工的情况下确保每个存储单元的介电强度的单元结构，并且控制微小的阈值分布。解决方案：非易失性半导体存储器件包括形成在半导体衬底S的表面层中的多个元件隔离绝缘膜DI，元件隔离绝缘膜DI中限定的多个元件区域AA，多个栅极配置包括通过隧道氧化膜10形成在半导体衬底S上的电荷存储层FG，以及分别通过栅极绝缘膜20形成在电荷存储层FG上的控制栅CG，形成在元件中的多个杂质扩散层IDL 区域AA，以便在它们之间的栅极配置之下夹住半导体衬底S的表面层，形成有氧化硅以便掩埋在栅极结构之间的绝缘膜60和形成有氮化硅的绝缘膜40，以便到来与门配置的侧壁接触。在非易失性半导体存储装置中，栅极绝缘膜40的基极与半导体基板S的表面分离电荷存储层FG的高度的至少一半以上。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2008235936A Non-volatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2008235936A
公开(公告)日：2008-10-02
申请号：JP2008137247
申请日：2008-05-26
申请人： Toshiba Corp , 株式会社東芝
发明人： YAEGASHI TOSHITAKE , SHIMIZU KAZUHIRO , ARITOME SEIICHI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device and a method of manufacturing the same, both of which are capable of reducing the number of manufacturing processes and has high-speed operability and high reliability.
SOLUTION: The non-volatile semiconductor memory device includes a memory cell, having a self-aligned two-layer gate structure which includes a gate insulating film formed on a semiconductor substrate, a first conductor 3 serving as a floating gate layer, a second conductor 7 serving as a control gate layer, and an insulation film 6 for electrically insulating the first conductor and the second conductor. The memory cell unit is constituted by connecting a plurality of the memory cells in series. A gate transistor is connected to the memory cell unit in series. A resistance element is constituted, by using the two-layer gate structure, the first conductor is used as a resistor, and the second conductor and the insulation film are removed, with respect to a region of a part of the first conductor.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：为了提供一种非易失性半导体存储器件及其制造方法，它们都能够减少制造工艺的数量并且具有高速可操作性和高可靠性。解决方案：非易失性半导体存储器件包括具有自对准双层栅极结构的存储单元，其包括形成在半导体衬底上的栅绝缘膜，用作浮栅的第一导体3，用作控制栅极层的第二导体7和用于使第一导体和第二导体电绝缘的绝缘膜6。存储单元单元通过串联连接多个存储单元来构成。栅极晶体管串联连接到存储单元单元。电阻元件通过使用双层栅极结构，第一导体用作电阻器，并且第二导体和绝缘膜相对于第一导体的一部分的区域被去除。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008103735A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2008103735A
公开(公告)日：2008-05-01
申请号：JP2007274305
申请日：2007-10-22
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU KAZUHIRO , ARAI FUMITAKA
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device, of which insulating film covering a stacked gate can reduce residue remaining in a shape of spacers on the both sides of an element isolation insulating film and increase contact area between contacts and semiconductor region.
SOLUTION: On a semiconductor substrate 31, an element isolating region embedded in a trench groove and a first semiconductor region electrically isolated by the element isolating region are formed. On the first semiconductor region, a charge-accumulating layer 33, a control gate 35 and a stacked gate, including a gate gap film 36 on the control gate 35, are formed through a tunnel-insulating film 32, and a bit-line contact 38 is embedded in an interlayer insulating film 44. The charge-accumulating layer 33 is arranged so that its side end surfaces line up with those of trench grooves. An element isolating region 51 is formed, up to a position higher than the surface of the semiconductor substrate 31, and the position of an element isolating region 52 under a control gate 35 is formed higher than that of the element isolating region 51 between the control gates 35.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决问题的方案：提供一种非易失性半导体存储装置，其中覆盖层叠栅极的绝缘膜可以减少残留在元件隔离绝缘膜两侧的间隔物的残留物，并增加触点之间的接触面积半导体区域。解决方案：在半导体衬底31上，形成嵌入沟槽中的元件隔离区和由元件隔离区电隔离的第一半导体区。在第一半导体区域上，通过隧道绝缘膜32形成电荷累积层33，控制栅极35和包括控制栅极35上的栅极间隙膜36的层叠栅极，并且位线接触 38被嵌入在层间绝缘膜44中。电荷蓄积层33被布置为使得其侧端表面与沟槽沟槽对齐。形成元件隔离区域51，直到高于半导体基板31的表面的位置，并且在控制栅极35下方的元件隔离区域52的位置形成为高于控制栅极35之间的元件隔离区域51的位置。门35。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2005136038A Nonvolatile semiconductor memory and its fabricating process 审中-公开
标题翻译：非易失性半导体存储器及其制造工艺
公开(公告)号：JP2005136038A
公开(公告)日：2005-05-26
申请号：JP2003368724
申请日：2003-10-29
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU KAZUHIRO
IPC分类号： H01L27/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory capable of enhancing the breakdown voltage of a high breakdown voltage transistor while reducing the cost, and to provide its fabricating process.
SOLUTION: An information memory element having first gate electrodes 3a/4a/5a/6a on a first gate insulating film 2a, a first diffusion layer 7a, and a first diffusion layer insulating film 8a formed thereon, an information operating element having second gate electrodes 3b/4b/5b/6b on a second gate insulating film 2b, a second diffusion layer 7b, and a second diffusion layer insulating film 8b formed thereon, and a signal potential generating element having third gate electrodes 3c/4c/5c/6c on a third gate insulating film 2c thicker than the first gate insulating film 2a and the second gate insulating film 2b, a third diffusion layer 7c, and a third diffusion layer insulating film 8c formed thereon are provided on a first conductivity type semiconductor substrate. The third diffusion layer insulating film 8c is thinner than the third gate insulating film 2c and having a thickness substantially equal to those of the first diffusion layer insulating film 8a and/or the second diffusion layer insulating film 8b.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供能够提高高击穿电压晶体管的击穿电压同时降低成本并提供其制造工艺的非易失性半导体存储器。解决方案：在第一栅极绝缘膜2a上形成有第一栅电极3a / 4a / 5a / 6a的信息存储元件，形成在其上的第一扩散层7a和第一扩散层绝缘膜8a，信息操作元件具有在第二栅极绝缘膜2b上形成的第二栅电极3b / 4b / 5b / 6b，形成在其上的第二扩散层7b和第二扩散层绝缘膜8b，以及具有第三栅极电极3c / 4c / 5c的信号电位产生元件在第一导电类型半导体衬底上设置有比第一栅极绝缘膜2a和第二栅极绝缘膜2b厚的第三栅极绝缘膜2c，形成在其上的第三扩散层7c和第三扩散层绝缘膜8c，。第三扩散层绝缘膜8c比第三栅极绝缘膜2c薄，其厚度基本上等于第一扩散层绝缘膜8a和/或第二扩散层绝缘膜8b的厚度。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2012114475A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2012114475A
公开(公告)日：2012-06-14
申请号：JP2012060561
申请日：2012-03-16
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU KAZUHIRO , HORII HIDEHITO
IPC分类号： H01L27/115 , H01L21/336 , H01L21/8247 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a cell structure capable of ensuring the breakdown voltage of a memory cell and capable of controlling accurate threshold distribution even in a microfabricated memory cell.SOLUTION: A nonvolatile semiconductor memory device comprises: a plurality of element isolation insulating films DI formed in a surface layer of a semiconductor substrate S; a plurality of element regions AA defined by the element isolation insulating films DI; a plurality of gate structures each including a charge storage layer FG formed on the semiconductor substrate S via a tunnel oxide film 10 and a control gate CG formed on the charge storage layer FG via a gate insulating film 20; a plurality of impurity diffusion layers IDL formed in the element regions AA so as to sandwich the surface layer of the semiconductor substrate S directly under the gate structures therebetween; insulating films 60 formed from oxide silicon so as to fill the gaps between the gate structures; and an insulating film 40 formed from nitride silicon so as to contact the side walls of the gate structures. The bottoms of the insulating film 40 are spaced apart from the surface of the semiconductor substrate S by at least a half or more of the height of the charge storage layers FG.
摘要翻译：解决的问题：提供能够确保存储单元的击穿电压并且即使在微制造的存储单元中也能够控制精确的阈值分布的单元结构。解决方案：非易失性半导体存储器件包括：形成在半导体衬底S的表面层中的多个元件隔离绝缘膜DI; 由元件隔离绝缘膜DI限定的多个元件区域AA; 多个栅极结构，每个栅极结构包括经由隧道氧化物膜10形成在半导体衬底S上的电荷存储层FG，以及经由栅极绝缘膜20形成在电荷存储层FG上的控制栅极CG; 形成在元件区域AA中的多个杂质扩散层IDL，以将半导体衬底S的表面层直接夹在它们之间的栅极结构之下; 由氧化硅形成的绝缘膜60，以填充栅极结构之间的间隙; 以及由氮化硅形成的与栅极结构的侧壁接触的绝缘膜40。绝缘膜40的底部与半导体基板S的表面间隔开电荷存储层FG的高度的至少一半以上。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2008270351A Non-volatile semiconductor storage device 审中-公开
标题翻译：非挥发性半导体存储器件
公开(公告)号：JP2008270351A
公开(公告)日：2008-11-06
申请号：JP2007108233
申请日：2007-04-17
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU KAZUHIRO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7883 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42336
摘要： PROBLEM TO BE SOLVED: To provide a structure to improve a coupling ratio of a memory cell, reduce fluctuation, and also improve breakdown voltage.
SOLUTION: A silicon substrate 1 is isolated into active regions 3 with STI2 that is formed by embedding a silicon oxide film 4. At the upper part of the active region 3, a tunnel insulating film 5, a floating gate electrode 6, an electrode insulating film 7, and a control gate electrode 8 are laminated. The end 4b at both ends of a recess 4a of the silicon oxide film 4 is set in a way that a film thickness d1 of the part opposed to the active region 3 and floating gate electrode 6 is almost equal to the film thickness d2 of the electrode insulating film 7. The bottom surface 4c at the center of the silicon oxide film 4 is formed as the concave part at a location lower than the upper surface of the silicon substrate 1.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种提高存储单元的耦合比的结构，减少波动，并且还提高击穿电压。解决方案：硅衬底1通过嵌入氧化硅膜4形成的STI2被隔离到有源区3中。在有源区3的上部，隧道绝缘膜5，浮栅电极6，层叠电极绝缘膜7和控制栅电极8。氧化硅膜4的凹部4a的两端的端部4b被设定为与有源区域3和浮栅电极6相对的部分的膜厚度d1几乎等于电极绝缘膜7.氧化硅膜4的中心处的底面4c在比硅衬底1的上表面低的位置处形成为凹部。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2007027571A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2007027571A
公开(公告)日：2007-02-01
申请号：JP2005210293
申请日：2005-07-20
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMIZU KAZUHIRO
IPC分类号： H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/417 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a structure robust against misalignment in photolithography.
SOLUTION: The semiconductor integrated circuit device comprises a signal electrode line BL arranged periodically, and a signal electrode line contact 13 arranged in a line at the same cycle with the signal electrode line BL in the ward line direction. The side surface of the signal electrode line BL contacts a first insulating material 14 and a second insulating material 15 laminated on the first insulating material 14. In the cross section in the word line direction, the diameter Dbtm at the part of the signal electrode line BL that contacts the signal electrode line contact 13 is smaller than the diameter Dtop at the top surface of the signal electrode line BL.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有抵抗光刻中的未对准的结构的半导体集成电路器件。解决方案：半导体集成电路器件包括周期性地布置的信号电极线BL以及与病区线方向上的信号电极线BL相同的周期配置成一行的信号电极线接点13。信号电极线BL的侧面接触层叠在第一绝缘材料14上的第一绝缘材料14和第二绝缘材料15.在字线方向的截面中，信号电极线的一部分的直径Dbtm 与信号电极线接点13接触的BL小于信号电极线BL顶面的直径Dtop。版权所有（C）2007，JPO＆INPIT

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