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1. 发明专利

JP2006080160A Electrostatic protective circuit 审中-公开
标题翻译：静电保护电路
公开(公告)号：JP2006080160A
公开(公告)日：2006-03-23
申请号：JP2004260130
申请日：2004-09-07
申请人： Toshiba Corp , 株式会社東芝
发明人： HIRAOKA TAKAYUKI
IPC分类号： H01L27/04 , H01L21/822 , H01L27/06 , H01L29/74
CPC分类号： H01L27/0262
摘要： PROBLEM TO BE SOLVED: To provide an electrostatic protective circuit capable of removing a trade-off relation by properly controlling discharge capability or turn-on time while improving latch-up resistance.
SOLUTION: The electrostatic protective circuit comprises a thyristor 3 for discharging excess electric charges existent between a first power supply terminal 1 and a second power supply terminal 2 at a lower electric potential than the first power supply terminal; a trigger circuit 7 for supplying a current for turning the thyristor 3 on; and an electrostatic discharge element 10 disposed between the first power supply terminal 1 and the second power supply terminal 2 and in parallel with the thyristor 3, having a higher current supply capability compared with that of the trigger circuit 7 at the same power supply inter-terminal voltage, and further changing to an on state in a shorter time than the turn-on time of the thyristor 3 connected to the trigger circuit 7 and at a voltage lower than the turn-on voltage of the thyristor.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够通过适当地控制放电能力或导通时间同时改善闭锁电阻来去除折衷关系的静电保护电路。解决方案：静电保护电路包括晶闸管3，用于在第一电源端子1和第二电源端子2之间以比第一电源端子更低的电位放电多余的电荷; 用于提供用于使晶闸管3导通的电流的触发电路7; 以及设置在第一电源端子1和第二电源端子2之间并与晶闸管3并联的静电放电元件10，其具有与在相同的电源供应端子2处的触发电路7相比具有更高的电流供应能力。并且在与连接到触发电路7的晶闸管3的接通时间相比更短的时间内进一步变为导通状态，并且电压低于晶闸管的导通电压。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2005142432A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005142432A
公开(公告)日：2005-06-02
申请号：JP2003378630
申请日：2003-11-07
申请人： Toshiba Corp , 株式会社東芝
发明人： HONJO ATSUSHI , HIRAOKA TAKAYUKI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L23/58 , H01L23/60 , H01L23/62 , H01L27/02 , H01L27/06 , H01L27/088
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To relax a design restriction of a thyristor and to decrease an area occupied by an integrated circuit device having an ESD-protection circuit in the integrated circuit comprising the ESD-protection circuit. SOLUTION: For instance, an intermediate node of a CR integration circuit 31 is at a Vdd electric potential by the agency of a resistor element 31a with no change in power voltage from a power supply PAD11. This turns off a PMOS transistor 33d. Accordingly, a feedback loop for causing a snap back is cut off to always cut off the thyristor part 33A. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了放松晶闸管的设计限制，并且减小在包括ESD保护电路的集成电路中具有ESD保护电路的集成电路装置占用的面积。解决方案：例如，CR积分电路31的中间节点由电阻元件31a的代理处于Vdd电位，电源电压PAD11没有变化。这将关断PMOS晶体管33d。因此，用于引起卡扣的反馈回路被切断以总是切断晶闸管部分33A。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2008258635A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008258635A
公开(公告)日：2008-10-23
申请号：JP2008105170
申请日：2008-04-14
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGURO KYOICHI , MIYANO KIYOTAKA , MIZUSHIMA ICHIRO , TSUNASHIMA YOSHITAKA , HIRAOKA TAKAYUKI , ARIKADO TSUNETOSHI
IPC分类号： H01L21/76 , H01L21/20 , H01L21/762 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which comprises an MOS type element in which a variation in element characteristic is controlled.
SOLUTION: The semiconductor devices is provided with an element isolation insulating film which is embedded in a semiconductor region of a substrate; a semiconductor layer of the semiconductor region in which elements are separated by the element isolation insulating film, and an upper portion of the semiconductor layer projects above the surface of the element isolation insulating film; an MOS type element in which a source-drain region, a gate insulating film and a gate electrode are formed in the semiconductor layer, and the gate electrode is formed on the element isolation insulating film in the section of a surface parallel to the direction of the width of a channel. The position of the upper surface of the semiconductor layer under the gate electrodes 20 nm or more higher than the position of the upper surface of the element isolation insulating film under the gate electrode.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种包括其元件特性变化被控制的MOS型元件的半导体器件。解决方案：半导体器件设置有元件隔离绝缘膜，其被嵌入在衬底的半导体区域中; 半导体区域的半导体层，其中元件被元件隔离绝缘膜分离，并且半导体层的上部突出在元件隔离绝缘膜的表面之上; 在半导体层中形成源极 - 漏极区域，栅极绝缘膜和栅电极的MOS型元件，并且栅极电极形成在元件隔离绝缘膜上的与通道的宽度。栅电极下方的半导体层的上表面的位置比栅电极下的元件隔离绝缘膜的上表面的位置高20nm以上。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2007067095A Electrostatic protective circuit 审中-公开
标题翻译：静电保护电路
公开(公告)号：JP2007067095A
公开(公告)日：2007-03-15
申请号：JP2005249898
申请日：2005-08-30
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE KENTARO , HIRAOKA TAKAYUKI , SATOU KOUICHI
IPC分类号： H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/092
CPC分类号： H01L27/0266
摘要： PROBLEM TO BE SOLVED: To provide an electrostatic protective circuit for protecting a buffer MOSFET while preventing a current from concentrating on the buffer MOSFET and eliminating wasteful power consumption when static electricity is discharged after detecting an electrostatic surge.
SOLUTION: The electrostatic protective circuit is provided with first/second power supply terminals 110, 112, an input/output terminal 111 for external connection, a buffer PMOSFET 108 for pulling up the input/output to high-level potential, a buffer NMOSFET 107 for pulling down the input/output to low-level potential, a rectifier cell 109 connected between the first/second power supply terminals, and a detector 101 for detecting the electrostatic surge by comparing potential between the input/output terminal and the first power supply terminal. When the electrostatic surge is detected by the detector, the buffer NMOSFET is turned off while controlling the gate potential of the buffer NMOSFET 107. Surge discharging is executed by parasitic bipolar transistors of the NMOSFETs 107, 119.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供用于保护缓冲MOSFET的静电保护电路，同时防止电流集中在缓冲MOSFET上，并且在检测到静电浪涌之后静电放电时消除浪费的功率消耗。
解决方案：静电保护电路设置有第一/第二电源端子110,112，用于外部连接的输入/输出端子111，用于将输入/输出提升到高电平电位的缓冲器PMOSFET 108，用于将输入/输出降低到低电平电位的缓冲器NMOSFET 107，连接在第一/第二电源端子之间的整流器单元109和用于通过比较输入/输出端子与第二电源端子之间的电位来检测静电浪涌的检测器101 第一电源端子。当检测器检测到静电浪涌时，缓冲器NMOSFET被截止，同时控制缓冲器NMOSFET 107的栅极电位。浪涌放电由NMOSFET 107,119的寄生双极晶体管执行。（C） 2007年，日本特许厅和INPIT

5. 发明专利

JP2009158621A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009158621A
公开(公告)日：2009-07-16
申请号：JP2007333302
申请日：2007-12-25
申请人： Toshiba Corp , 株式会社東芝
发明人： HIRAOKA TAKAYUKI , UTSUMI KUNIAKI , HONDA KENJI , KOJIMA TSUTOMU
IPC分类号： H01L21/8234 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/088 , H01L27/092
CPC分类号： H01L21/823418 , H01L27/0266 , H01L27/088 , H01L29/0847 , H01L29/105 , H01L29/1083 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： PROBLEM TO BE SOLVED: To easily enhance an ESD discharging performance in a MOSFET type ESD protection element having an LDD structure.
SOLUTION: Formed is, just under the silicide block 51a of an HV ESD protection device 1A, a diffusion layer resistance region 29a of the same junction depth as those of LDD diffusion layers 26a and 27a for forming an extension region. Just under the silicide block 51b of an LV ESD protection device 1B, a diffusion resistance region 29b of the same junction depth as the LDD diffusion layers 26a and 27a, and the diffusion layer resistance region 29a, to be formed simultaneously with the LDD diffusion layers 26a and 27a, and diffusion layer resistance region 29a of the HV ESD protection device 1A, is provided.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：为了容易地提高具有LDD结构的MOSFET型ESD保护元件的ESD放电性能。解决方案：形成在HV ESD保护装置1A的硅化物块51a正下方的与用于形成延伸区域的LDD扩散层26a和27a相同的结深度的扩散层电阻区域29a。在LV ESD保护器件1B的硅化物块51b的正下方，与LDD扩散层同时形成的与LDD扩散层26a和27a以及扩散层电阻区域29a相同的结深度的扩散电阻区域29b 26a和27a以及HV ESD保护装置1A的扩散层电阻区域29a。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2009099684A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009099684A
公开(公告)日：2009-05-07
申请号：JP2007268228
申请日：2007-10-15
申请人： Toshiba Corp , 株式会社東芝
发明人： HIRAOKA TAKAYUKI
IPC分类号： H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing a deterioration of a latch-up resistance, even if a power supply protective circuit and an input and output circuit are adjacently or closely arranged.
SOLUTION: To arrangements of an N
+ diffusion layer 221 and a P
+ diffusion layer 222 of an input and output circuit 2, a P
+ diffusion layer 211, an N
+ diffusion layer 212, a P
+ diffusion layer 213 and an N
+ diffusion layer 214 forming a thyristor 11 of a power supply protective circuit 1 are lined up in the same row adjusted to a row of the N
+ diffusion layer 221 and the P
+ diffusion layer 222. An N
+ diffusion layer 312 connected to a VSS and used as a cathode of the thyristor 11 is arranged in a position far from a P
+ diffusion layer 321 connected to an I/O within the input and output circuit 2. A P
+ diffusion layer 313 connected to a VDD and used as an anode of the thyristor 11 is arranged in a near position from an N
+ diffusion layer 322 connected to the VDD within the input and output circuit 2.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：即使电源保护电路和输入和输出电路相邻或紧密地布置，也提供能够防止闩锁电阻的劣化的半导体器件。解决方案：对于输入和输出电路2的N + 扩散层221和P + 扩散层222的布置，P / SP>扩散层211，N + 扩散层212，P + 扩散层213和N + SP扩散层214 电源保护电路1的晶闸管11被排列在调整到N + 扩散层221和P +扩散层222的一行的同一行中。连接到VSS并用作晶闸管11的阴极的扩散层312布置在远离连接到I / O的P + 扩散层321的位置， O连接到VDD并用作晶闸管11的阳极的AP + 扩散层313被布置在距离N + 扩散层322连接到输入和输出电路2内的VDD。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2004266291A Semiconductor device 审中-公开
公开(公告)号：JP2004266291A
公开(公告)日：2004-09-24
申请号：JP2004137525
申请日：2004-05-06
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGURO KYOICHI , MIYANO KIYOTAKA , MIZUSHIMA ICHIRO , TSUNASHIMA YOSHITAKA , HIRAOKA TAKAYUKI , ARIKADO TSUNETOSHI
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, having a MOS device in which the variations of the element characteristics is suppressed. SOLUTION: The semiconductor device comprises an element isolation insulating film which is embedded at semiconductor region of a substrate and has upper part projecting over the surface of the semiconductor region, semiconductor layers of the semiconductor region which is separated in element with the element isolation insulating film, and the MOS-type device formed in this semiconductor layers. The device is characterized in that upper surface position of the element isolation insulating film against the substrate is higher than that of the semiconductor layers against the substrate by 3 times or more of film thickness of a gate insulating film of the MOS-type device. COPYRIGHT: (C)2004,JPO&NCIPI

8. 发明专利

JP2014003072A Electrostatic protection circuit, and semiconductor device 有权
标题翻译：静电保护电路和半导体器件
公开(公告)号：JP2014003072A
公开(公告)日：2014-01-09
申请号：JP2012135912
申请日：2012-06-15
申请人： Toshiba Corp , 株式会社東芝
发明人： KUSHIBE HIDEFUMI , HIRAOKA TAKAYUKI
IPC分类号： H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092 , H03K17/22
CPC分类号： H02H9/046
摘要： PROBLEM TO BE SOLVED: To provide an electrostatic protection circuit capable of reducing influences of a state of a power supply on an electrostatic protection operation.SOLUTION: An electrostatic protection circuit comprises: a resistor and a capacitor connected in series between a power supply terminal and a ground terminal; and a second capacitor having one end connected to at least any one of an output of a first inverter, an output of a second inverter, and a gate of a MOS transistor for protection, and the other end connected to any one of the power supply terminal and the ground terminal.
摘要翻译：要解决的问题：提供能够减少电源状态对静电保护操作的影响的静电保护电路。解决方案：静电保护电路包括：电阻器和电容器，串联连接在电源端子和地面终端; 以及第二电容器，其一端连接到第一反相器的输出，第二反相器的输出和用于保护的MOS晶体管的栅极中的至少任一个，并且另一端连接到电源中的任一个端子和接地端子。

9. 发明专利

JP2011054699A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2011054699A
公开(公告)日：2011-03-17
申请号：JP2009201257
申请日：2009-09-01
申请人： Toshiba Corp , 株式会社東芝
发明人： HIRAOKA TAKAYUKI
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822
CPC分类号： H01L27/0255 , H01L2224/05554
摘要： PROBLEM TO BE SOLVED: To stably protect an internal circuit from an electrostatic breakdown while preventing an element area from increasing even when a surge voltage is applied to power supply lines via an input or output circuit. SOLUTION: Power protection elements 6a-6d are arranged in gaps between input and output cells 3c-3f, respectively, and each of the diode strings S2-S5 connected between the power supply lines 7, 8 is used as power protection elements 6a-6d. COPYRIGHT: (C)2011,JPO&INPIT

10. 发明专利

JP2008147376A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008147376A
公开(公告)日：2008-06-26
申请号：JP2006332153
申请日：2006-12-08
申请人： Toshiba Corp , 株式会社東芝
发明人： HIRAOKA TAKAYUKI
IPC分类号： H01L21/822 , H01L27/04 , H01L27/06
CPC分类号： H01L27/0255 , H01L23/5286 , H01L24/06 , H01L2924/1301 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an electrostatic discharge protection circuit which has a high surface efficiency in the peripheral region of a semiconductor chip. SOLUTION: The electrostatic discharge protection circuit includes a plurality of power pads 601 to 603 disposed in the peripheral region of a semiconductor chip for different power voltages VSS, VDD1, VDD2 to be allocated thereto, a first power wiring line 604 commonly connected to a plurality of the first power pads 601, a second power wiring line 605 commonly connected to a plurality of the second power pads 602, a third power wiring line 606 electrically connected commonly to a plurality of the third power pads 603, a plurality of first static electricity protection circuit regions 607 connected to both ends of the first and second power wiring lines, and a plurality of second static electricity protection circuit regions 612 connected to both ends of the second and third power wiring lines. Static electricity protection circuit regions 608 each having one of the first static electricity protection circuit regions and one of the second static electricity protection circuit regions connected in series included therein are disposed to be associated with the respective power pads. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在半导体芯片的周边区域具有高表面效率的静电放电保护电路。解决方案：静电放电保护电路包括设置在半导体芯片的外围区域中的多个电源焊盘601至603，用于分配不同的电源电压VSS，VDD1，VDD2;第一电源线604共同连接耦合到多个第一电源焊盘601，共同连接到多个第二电源焊盘602的第二电力布线605，与多个第三电源焊盘603共同电连接的第三电力布线606，多个连接到第一和第二电力线路两端的第一静电保护电路区域607以及连接到第二和第三电力线路两端的多个第二静电保护电路区域612。每个具有第一静电保护电路区域和串联连接的第二静电保护电路区域之一的静电保护电路区域608被设置为与相应的电源焊盘相关联。版权所有（C）2008，JPO＆INPIT

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