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1. 发明专利

JP2013150092A Interface circuit and semiconductor memory device 审中-公开
标题翻译：接口电路和半导体存储器件
公开(公告)号：JP2013150092A
公开(公告)日：2013-08-01
申请号：JP2012007811
申请日：2012-01-18
申请人： Toshiba Corp , 株式会社東芝
发明人： KUSHIBE HIDEFUMI
IPC分类号： H03K19/0175 , H03K19/0944
摘要： PROBLEM TO BE SOLVED: To provide an interface circuit capable of operating at higher speed in a wide power-supply voltage range.SOLUTION: An interface circuit includes: a first MOS transistor of a first conductivity type having a source and a back gate connected to a first power-supply terminal to which a first power-supply voltage is applied, and having a drain connected to an output terminal outputting an output signal; a second MOS transistor of a second conductivity type having a drain connected to the output terminal, and having a source and a back gate connected to a fixed potential; and a third MOS transistor of the second conductivity type having a drain connected to the first power-supply terminal and having a source and a back gate connected to the output terminal.
摘要翻译：要解决的问题：提供能够在宽电源电压范围内以更高速度运行的接口电路。解决方案：接口电路包括：第一导电类型的第一MOS晶体管，其具有源极和后栅极连接到第一电源端子，施加有第一电源电压，并且具有连接到输出端子的漏极输出输出信号; 第二导电类型的第二MOS晶体管，其漏极连接到输出端子，并具有连接到固定电位的源极和后栅极; 以及第二导电类型的第三MOS晶体管，其漏极连接到第一电源端子，并且具有连接到输出端子的源极和后栅极。

2. 发明专利

JP2010192583A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010192583A
公开(公告)日：2010-09-02
申请号：JP2009033860
申请日：2009-02-17
申请人： Toshiba Corp , 株式会社東芝
发明人： KUSHIBE HIDEFUMI
IPC分类号： H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing unwanted radiation.
SOLUTION: The semiconductor device has a first resistance element connected between a first ground terminal and a second ground terminal, i.e. between a ground connection of an output circuit to which the first ground terminal is connected and a ground connection of a first input circuit to which the second ground terminal is connected.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供能够减少不需要的辐射的半导体器件。解决方案：半导体器件具有连接在第一接地端子和第二接地端子之间的第一电阻元件，即在与第一接地端子连接的输出电路的接地连接和第一接地端子的接地连接第二接地端子所连接的电路。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2014003072A Electrostatic protection circuit, and semiconductor device 有权
标题翻译：静电保护电路和半导体器件
公开(公告)号：JP2014003072A
公开(公告)日：2014-01-09
申请号：JP2012135912
申请日：2012-06-15
申请人： Toshiba Corp , 株式会社東芝
发明人： KUSHIBE HIDEFUMI , HIRAOKA TAKAYUKI
IPC分类号： H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092 , H03K17/22
CPC分类号： H02H9/046
摘要： PROBLEM TO BE SOLVED: To provide an electrostatic protection circuit capable of reducing influences of a state of a power supply on an electrostatic protection operation.SOLUTION: An electrostatic protection circuit comprises: a resistor and a capacitor connected in series between a power supply terminal and a ground terminal; and a second capacitor having one end connected to at least any one of an output of a first inverter, an output of a second inverter, and a gate of a MOS transistor for protection, and the other end connected to any one of the power supply terminal and the ground terminal.
摘要翻译：要解决的问题：提供能够减少电源状态对静电保护操作的影响的静电保护电路。解决方案：静电保护电路包括：电阻器和电容器，串联连接在电源端子和地面终端; 以及第二电容器，其一端连接到第一反相器的输出，第二反相器的输出和用于保护的MOS晶体管的栅极中的至少任一个，并且另一端连接到电源中的任一个端子和接地端子。

4. 发明专利

JP2006039861A Series regulator circuit 审中-公开
标题翻译：系列调节器电路
公开(公告)号：JP2006039861A
公开(公告)日：2006-02-09
申请号：JP2004217569
申请日：2004-07-26
申请人： Toshiba Corp , 株式会社東芝
发明人： KUSHIBE HIDEFUMI
IPC分类号： G05F1/56
摘要： PROBLEM TO BE SOLVED: To provide a series regulator circuit capable of achieving the enhancement of AC (Alternating Current) characteristics.
SOLUTION: The series regulator circuit comprises: a current source circuit 10 which generates a first operating current; an amplifier circuit 20 which operates after being supplied with the first operating current, compares a reference voltage with a feedback voltage after being supplied with them and outputs a comparison result voltage corresponding to the comparison result; an output circuit 30 having an output section which outputs an output current corresponding to the comparison result voltage after being supplied the comparison result voltage and a feedback voltage generation section which generates a feedback voltage corresponding to the output current and feeds it to the amplifier circuit 20; and an addition circuit 40 having an output extraction section which extracts part of the output current outputted by the output section and an addition section which adds a second operating current corresponding to part of the output current and feeds it to the amplifier circuit 20.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供能够实现AC（交流）特性的增强的串联调节器电路。串联调节器电路包括：电流源电路10，其产生第一工作电流; 在被提供第一工作电流之后工作的放大器电路20将参考电压与提供它们之后的反馈电压进行比较，并输出与比较结果相对应的比较结果电压; 输出电路30，其具有输出部分，其在提供比较结果电压之后输出与比较结果电压相对应的输出电流;以及反馈电压产生部，其产生与输出电流相对应的反馈电压并将其馈送到放大器电路20 ; 以及加法电路40，具有输出提取部分，该输出提取部分提取由输出部分输出的输出电流的一部分;以及相加部分，其加上与输出电流的一部分相对应的第二工作电流并将其馈送到放大器电路20.
版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2003324322A Amplifying apparatus 审中-公开
标题翻译：放大装置
公开(公告)号：JP2003324322A
公开(公告)日：2003-11-14
申请号：JP2002127564
申请日：2002-04-26
申请人： Toshiba Corp , 株式会社東芝
发明人： YAGI TOSHIHIRO , KUSHIBE HIDEFUMI
IPC分类号： H03F1/00
摘要： PROBLEM TO BE SOLVED: To obtain an amplifying apparatus which reduces power-ON noise and corrects variations of noise due to manufacture variance and temperature and source voltage variations.
SOLUTION: The amplifying apparatus is equipped with a power-on noise reducing circuit which outputs a control signal in the timing to the turning-off operation of a power switch for switching electric power supplied to an amplifier, outputs a reference voltage outputted from a reference potential generating circuit to an output terminal of the amplifier, and outputs a rapid rising voltage signal in the timing to the input of the control signal to adjust the turning-on timing of the amplifier.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：获得降低通电噪声并且由于制造方差和温度和源极电压变化而校正噪声变化的放大装置。解决方案：放大装置配备有电源噪声降低电路，其在定时将输出控制信号输出到用于切换提供给放大器的电力的电源开关的关断操作，输出输出的参考电压从参考电位产生电路到放大器的输出端子，并且将该定时中的快速上升电压信号输出到控制信号的输入端，以调整放大器的导通时间。版权所有（C）2004，JPO

6. 发明专利

JP2013140518A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2013140518A
公开(公告)日：2013-07-18
申请号：JP2012000723
申请日：2012-01-05
申请人： Toshiba Corp , 株式会社東芝
发明人： KUSHIBE HIDEFUMI
IPC分类号： G05F1/56 , H01L21/822 , H01L27/04
CPC分类号： G05F1/565 , G05F1/575
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that can operate as one of a series regulator and a power supply switch according to a power supply voltage.SOLUTION: If a power supply voltage is equal to or more than a first specified value, a semiconductor integrated circuit activates an amplifier device to output a control voltage for controlling the operation of a main MOS transistor from a second output terminal to a gate of the main MOS transistor so that a monitor voltage and a reference voltage become equal to each other, and also turns a first switch element OFF. If the power supply voltage is less than the first specified value, the semiconductor integrated circuit deactivates the amplifier device to set the second output terminal to a high impedance and also turns the first switch element ON.
摘要翻译：要解决的问题：提供可以根据电源电压作为串联调节器和电源开关之一操作的半导体集成电路。解决方案：如果电源电压等于或大于第一指定值，半导体集成电路激活放大器装置以输出用于控制主MOS晶体管从主MOS晶体管的第二输出端到栅极的操作的控制电压，使得监视电压和参考电压彼此相等，并且还将第一开关元件断开。如果电源电压小于第一规定值，则半导体集成电路使放大器装置去激活，将第二输出端子设定为高阻抗，并使第一开关元件导通。

7. 发明专利

JP2010192584A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010192584A
公开(公告)日：2010-09-02
申请号：JP2009033865
申请日：2009-02-17
申请人： Toshiba Corp , 株式会社東芝
发明人： KUSHIBE HIDEFUMI
IPC分类号： H01L21/822 , H01L23/12 , H01L27/04 , H05K9/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing unwanted radiation. SOLUTION: The semiconductor device 100 includes: a semiconductor substrate 1; a first power supply terminal 2 to which a first power supply voltage VDD1 is supplied; a first ground terminal 3 used for connection to a ground; a first semiconductor integrated circuit 4 connected between the first power supply terminal 2 and the first ground terminal 3, formed on the semiconductor substrate 1 and configured by a multilayer wiring; and a conductive first flat plate 5 connected to either the first ground terminal 3 or the first power supply terminal 2, formed on the first semiconductor integrated circuit 4 so as to cover the entire upper part of the first semiconductor integrated circuit and having a plurality of first through-holes 5a on a surface parallel to the substrate surface of the semiconductor substrate 1. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供能够减少不需要的辐射的半导体器件。解决方案：半导体器件100包括：半导体衬底1; 提供第一电源电压VDD1的第一电源端子2; 用于连接地面的第一接地端子3; 连接在第一电源端子2和第一接地端子3之间的第一半导体集成电路4，形成在半导体衬底1上并由多层布线构成; 以及连接到第一接地端子3或第一电源端子2上的导电的第一平板5，形成在第一半导体集成电路4上，以覆盖第一半导体集成电路的整个上部，并且具有多个在与半导体基板1的基板表面平行的表面上的第一通孔5a。（C）2010，JPO＆INPIT

8. 发明专利

JPH05136358A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH05136358A
公开(公告)日：1993-06-01
申请号：JP29732591
申请日：1991-11-13
申请人： TOSHIBA CORP
发明人： KUSHIBE HIDEFUMI , USHIKU YUKIHIRO
IPC分类号： H01L21/8238 , G11C11/409 , H01L27/092 , H03K19/003 , H03K19/0175
摘要： PURPOSE:To restrain a switching noise caused by an inductance component by a method wherein the phase of the output of a first buffer circuit is constituted to be completely opposite at a rise and at a fall and the phase of the operation of a second buffer circuit is constituted to be completely opposite to that of the first buffer circuit. CONSTITUTION:One end of a load capacity is connected to the output end of a buffer circuit 7; a power-supply voltage VSS is supplied to the other end of the load capacity 8. The buffer circuit 7 is constituted so as to be operated at a phase which is completely opposite to that of a buffer circuit 4. That is to say, the input signal of the buffer circuit 7 is the inverse of a signal Vin of the signal Vin of the buffer circuit 4. A bypass capacity 6 is connected in parallel with the buffer circuits 4, 7, and power-supply voltages VDD1, VSS1 inside a circuit device are applied to it. Inductances 2, 10 caused by lead wires or the like in a package exist between the external power supply and the internal power supply of the circuit device. A noise generated in the power supply is offset by adding the buffer circuit 7 and the load capacity 8 whose phase is opposite.

9. 发明专利

JP2002208821A POWER AMPLIFIER START CIRCUIT DEVICE AND METHOD FOR CONTROLLING THE SAME 失效
公开(公告)号：JP2002208821A
公开(公告)日：2002-07-26
申请号：JP2000403373
申请日：2000-12-28
申请人： TOSHIBA CORP
发明人： YAGI TOSHIHIRO , KUSHIBE HIDEFUMI
IPC分类号： H04R3/00 , H03F1/00 , H03F3/181
摘要： PROBLEM TO BE SOLVED: To provide a power amplifier starting circuit device which suppresses increase in the drive current and can also start a power amplifier output slowly in a small area. SOLUTION: This power amplifier start circuit device is provided with a 1st switch connected to the negative input of a power amplifier, a capacitor and a 1st resistor connected to the positive input node of the power amplifier, a 2nd switch connected in parallel with the capacitor, a 3rd switch connected between the 1st resistor and an analog reference voltage generation circuit, and a 4th switch connected between the output node of the power amplifier and a ground potential. Control is carried so that the 1st and 3rd switches are turned off in an initial state, the 2nd a 4th switches are also turned on, the power amplifier is turned on next, the 3rd switch is subsequently turned on, and the 2nd and 4th switched are turned off.

10. 发明专利

JPH07170157A VOLTAGE CONTROLLED OSCILLATION CIRCUIT DEVICE 失效
公开(公告)号：JPH07170157A
公开(公告)日：1995-07-04
申请号：JP31477893
申请日：1993-12-15
申请人： TOSHIBA CORP
发明人： KUSHIBE HIDEFUMI
IPC分类号： H03K3/354
摘要： PURPOSE:To obtain a voltage controlled oscillation circuit device producing a voltage fully swinging at an upper limit and a lower limit of a high potential power source voltage and a low potential power source voltage even when a load having a high input capacitance is connected to its output terminal. CONSTITUTION:N-sets of constant current operation CMOS inverters 10-NO of the same rating are connected in a ring to form an oscillation circuit. When a load is connected to an output terminal of a specific CMOS inverter, pseudo loads 15, 25 having an input capacitance Cd of Cd>={Cload-(N-2).CG/(N-1)} are connected to output terminals of all the CMOS inverters except that to which the load is connected, where Cload is a capacitance of the load and CG is an input capacitance of the CMOS inverter.

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