专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2013225363A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2013225363A
公开(公告)日：2013-10-31
申请号：JP2012097806
申请日：2012-04-23
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMATA YOSHIHIKO , TABATA KOJI , HAMANO TOMOYUKI
IPC分类号： G11C16/06 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device that can accelerate charging while suppressing an overshoot of a potential of a source node.SOLUTION: A semiconductor memory device comprises: an array 1 in which first and second blocks, where memory cells on a well are connected in series and which include NAND strings connected to sources, are disposed; a source line driver 7 that has a first node, CELSRC, connected to sources and charges/discharges potentials of the sources and the well; and voltage control circuits 61, 62 and 63 for controlling charging/discharge of the first node, CELSRC. The voltage control circuits 61, 62 and 63 comprise: boosters 62 and 63 that boost the potential of the well at the time of read-out operation and stop boosts of the sources and the well when detecting the potentials exceeding a first specified value; and pull-down driver 61 for controlling so as to discharge the potential of the first node, CELSRC, when the potentials of the sources exceed a second specified value.
摘要翻译：要解决的问题：提供一种半导体存储器件，其可以在抑制源极节点的电位的过冲的同时加速充电。解决方案：半导体存储器件包括：阵列1，其中第一和第二块，其中存储单元串联连接并且包括连接到源的NAND串，被布置; 源线路驱动器7，其具有连接到源极并且对源极和阱的电位进行充电/放电的第一节点CELSRC; 以及用于控制第一节点CELSRC的充电/放电的电压控制电路61,62和63。电压控制电路61,62和63包括：增强器62和63，其在读出操作时升高阱的电位，并且当检测到超过第一指定值的电位时停止源极和阱的升压; 和下拉驱动器61，用于控制，以便当源的电位超过第二指定值时，排出第一节点CELSRC的电位。

2. 发明专利

JP2012069180A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2012069180A
公开(公告)日：2012-04-05
申请号：JP2010211269
申请日：2010-09-21
申请人： Toshiba Corp , 株式会社東芝
发明人： TABATA KOJI , SAITO SAKATOSHI , ABE MITSUHIRO , HARA NORIMASA
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G06F11/1048 , G11C7/1006 , G11C2029/0411
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device having a small area.SOLUTION: The semiconductor storage device includes a buffer 13 including latch circuits. Multiple latch circuit groups are constructed of a prescribed number of latch circuits, and each latch circuit in each latch circuit group is connected in common to a common line via transfer circuits. An error correction part 3 is connected to the common lines, and detects and corrects error bits contained in supplied data. A data transfer control part 22 causes data to be read into the buffer from a memory cell subject to verification, and causes all stored data in latch circuits in each latch circuit group to be read into a corresponding common line as partial verification data, sequentially over a prescribed number of latch circuit groups. A verification control part 21 causes the error correction part to detect errors in verification data composed of a set of the partial verification data from each of the prescribed number of latch circuit groups, to judge existence of fail-bits in the verification data.
摘要翻译：解决的问题：提供一种面积小的半导体存储装置。解决方案：半导体存储装置包括具有锁存电路的缓冲器13。多个锁存电路组由规定数量的锁存电路构成，并且每个锁存电路组中的每个锁存电路通过传输电路共同连接到公共线。误差校正部分3连接到公共线，并且检测和校正所提供的数据中包含的错误位。数据传送控制部分22使数据从经过验证的存储单元读入缓冲器，并且将每个锁存电路组中的锁存电路中的所有存储数据作为部分验证数据读取到对应的公共线中，规定数量的锁存电路组。验证控制部分21使纠错部分检测来自每个规定数量的锁存电路组的部分验证数据的集合的验证数据中的错误，以判断验证数据中的故障位的存在。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2013232264A Semiconductor memory device and reading method therefor 审中-公开
标题翻译：半导体存储器件及其读取方法
公开(公告)号：JP2013232264A
公开(公告)日：2013-11-14
申请号：JP2012104083
申请日：2012-04-27
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMATA YOSHIHIKO , SAKO MARIO , TABATA KOJI , HAMANO TOMOYUKI
IPC分类号： G11C16/06 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which reduces read errors of data.SOLUTION: The semiconductor memory device includes: a first transistor 24 to which a voltage VHSA (which is first voltage VDD) is supplied and which can supply first current to a bit line; a detection section SEN which detects the current passing through the bit line and reads held data in a memory cell connected to the bit line; and a second transistor 30 which can transfer any one of the first voltage VDD and a second voltage VX2SA larger than the first voltage, to the detection section. The second transistor charges the detection section SEN to any one of the first voltage VDD and the second voltage VX2SA while passing the first current to the bit line.
摘要翻译：要解决的问题：提供减少数据读取误差的半导体存储器件。解决方案：半导体存储器件包括：提供电压VHSA（其为第一电压VDD）的第一晶体管24，并且可以提供第一电流到一点点检测部分SEN，其检测通过位线的电流，并且读取与位线连接的存储单元中的保持数据; 以及能够将大于第一电压的第一电压VDD和第二电压VX2SA中的任一个传送到检测部的第二晶体管30。第二晶体管将检测部分SEN充电到第一电压VDD和第二电压VX2SA中的任何一个，同时将第一电流传送到位线。

4. 发明专利

JP2013225365A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2013225365A
公开(公告)日：2013-10-31
申请号：JP2012097925
申请日：2012-04-23
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMATA YOSHIHIKO , YOKOTA HIROKO , TABATA KOJI , HAMANO TOMOYUKI
IPC分类号： G11C16/06 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of reading data at a threshold level on a further negative side.SOLUTION: A semiconductor memory device comprises: a memory cell array in which memory cells capable of storing data are connected in series, strings having a source and drain are included, and each of the strings is connected in common through the source; each of the NAND strings; bit lines that are connected through corresponding drains; a sense amplifier (6) that includes a first transistor (BLX) and a second transistor (BLC) that are connected in series to each other and charge the bit lines to a first voltage (Vblc) when reading data from the memory cells; and a voltage generation circuit that supplies the sum of the first voltage and a second voltage to the gates of the first and second transistors while supplying the second voltage (CELSRC=VDD-Vblc) to the sources.
摘要翻译：要解决的问题：提供能够在另一负侧读取阈值电平的数据的半导体存储器件。解决方案：半导体存储器件包括：存储单元阵列，其中能够存储数据的存储器单元串联连接，包括源极和漏极的串，并且每个串通过源共同连接; 每个NAND串; 通过相应的排水管连接的位线; 读出放大器（6），其包括在从存储器单元读取数据时彼此串联连接并将位线充电至第一电压（Vblc）的第一晶体管（BLX）和第二晶体管（BLC）以及电压产生电路，其将第一电压和第二电压的和提供给第一和第二晶体管的栅极，同时向源提供第二电压（CELSRC = VDD-Vblc）。

5. 发明专利

JP2013225364A Semiconductor memory device and operation method for the same 审中-公开
标题翻译：半导体存储器件及其操作方法
公开(公告)号：JP2013225364A
公开(公告)日：2013-10-31
申请号：JP2012097807
申请日：2012-04-23
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMATA YOSHIHIKO , TABATA KOJI , KOGA MITSUHIRO , HAMANO TOMOYUKI , YOKOTA HIROKO
IPC分类号： G11C16/06 , G11C16/02
CPC分类号： G11C29/04 , G06F11/1008 , G11C16/0483 , G11C16/26 , G11C29/42
摘要： PROBLEM TO BE SOLVED: To provide a sense amplifier that enables a high-speed XOR operation while maintaining a size of a circuit area.SOLUTION: A semiconductor memory device comprises: a memory cell array 10 including strings in which memory cells capable of holding data are connected in series; a sense amplifier 12 that is provided with a first node SEN for detecting an amount of currents flowing through the memory cells and includes a first latch SDL and a second latch XDL for storing results detected by the first node SEN; a control section, sequencer 15, including a transfer control section that causes a first operation OR and a second operation NAND to be performed by using the data read-out from the memory cells and stored in the first latch SDL and the second latch XDL, subsequently causes a third operation AND to be performed by first results obtained by the first operation OR and second results obtained by the second operation NAND and determines whether or not erroneous reading-out with respect to the data read-out exists; and a detection section 12-3 for storing the third operation by the control section.
摘要翻译：要解决的问题：提供一种能够在保持电路面积的大小的同时进行高速异或运算的读出放大器。解决方案：半导体存储器件包括：存储单元阵列10，其包括能够保存数据的存储单元的串串联连接读出放大器12，其具有用于检测流过存储单元的电流量的第一节点SEN，并且包括第一锁存器SDL和第二锁存器XDL，用于存储由第一节点SEN检测到的结果; 控制部分，定序器15，包括通过使用从存储器单元读出并存储在第一锁存器SDL和第二锁存器XDL中的数据来执行第一操作OR和第二操作NAND的传送控制部分，随后通过第一操作OR获得的第一结果和通过第二操作NAND获得的第二结果执行第三操作AND并确定是否存在关于数据读出的错误读出; 以及用于存储控制部分的第三操作的检测部分12-3。

6. 发明专利

JP2014186763A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2014186763A
公开(公告)日：2014-10-02
申请号：JP2013059144
申请日：2013-03-21
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMATA YOSHIHIKO , TABATA KOJI , HAMANO TOMOYUKI
IPC分类号： G11C16/06 , G11C16/02
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/24
摘要： PROBLEM TO BE SOLVED: To provide a sense amplifier capable of performing a write operation and simultaneously performing external transfer of a verification result.SOLUTION: A nonvolatile semiconductor memory device is provided with: a memory cell array that includes memory cells; and a sense amplifier that includes a latch unit (SDL) capable of holding write data and a detection unit (DTCT) and transfers either one of a first voltage (0 V) or a second voltage (VDDSA), which is higher than the first voltage, to a bit line according to the write data. The sense amplifier transfers either one of the first voltage or second voltage as a third voltage to the bit line according to a verification result and simultaneously transfers the third voltage to the detection unit.
摘要翻译：要解决的问题：提供一种能够执行写入操作并同时执行验证结果的外部传送的读出放大器。解决方案：非易失性半导体存储器件设置有：存储单元阵列，其包括存储单元; 以及包括能够保持写入数据的锁存单元（SDL）和检测单元（DTCT）的读出放大器，并且将第一电压（0V）或第二电压（VDDSA）中的任一个高于第一电压，根据写入数据到位线。感测放大器根据验证结果将第一电压或第二电压中的任一个作为第三电压转移到位线，并将第三电压同时传送到检测单元。

7. 发明专利

JP2014182845A Nonvolatile semiconductor memory device and write method for the same 审中-公开
标题翻译：非易失性半导体存储器件及其相同的写入方法
公开(公告)号：JP2014182845A
公开(公告)日：2014-09-29
申请号：JP2013055615
申请日：2013-03-18
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMATA YOSHIHIKO , TABATA KOJI
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3459
摘要： PROBLEM TO BE SOLVED: To provide a sense amplifier that can improve reliability while decreasing a circuit area.SOLUTION: A nonvolatile semiconductor memory device comprises a first transistor (VPRE), a latch circuit (SDL), a detection section (SEN, Tr28) capable of holding a first value, a second transistor (STB), and a third transistor (XXL). The latch circuit includes a fourth transistor (STI). After a first voltage is transferred to a bit line, the first transistor transfers as the value a first result (verification result, e.g. LP) obtained by turned on the third transistor twice to the latch circuit via the second transistor and the fourth transistor, and again transfers, as a voltage according to the value, a ground potential or a second voltage(VQPW) higher than the ground potential and lower than an internal voltage (VDD) to the bit line.
摘要翻译：解决方案：提供一种能够在减小电路面积的同时提高可靠性的读出放大器。解决方案：一种非易失性半导体存储器件，包括第一晶体管（VPRE），锁存电路（SDL），检测部分（SEN，Tr28）能够保持第一值，第二晶体管（STB）和第三晶体管（XXL）。锁存电路包括第四晶体管（STI）。在将第一电压转移到位线之后，第一晶体管将通过第二晶体管和第四晶体管接通第三晶体管两次获得的第一结果（验证结果（例如LP））转换为锁存电路，再次将与接地电位相比的接地电位或第二电压（VQPW）作为根据该值的电压传送到位线的内部电压（VDD）以下。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式