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1. 发明专利

JP2012038818A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012038818A
公开(公告)日：2012-02-23
申请号：JP2010175693
申请日：2010-08-04
申请人： Toshiba Corp , 株式会社東芝
发明人： KUTSUKAKE HIROYUKI , KATO TOKO , FUKUDA KOICHI , WATANABE YOSHIHISA , MASUDA KAZUNORI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H02M3/07
CPC分类号： H01L27/11526 , H01L27/11521 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To reduce the occupied area of the region for forming capacitors.SOLUTION: A semiconductor device comprises: a semiconductor region AAC provided in a semiconductor substrate 10; and a capacitor group including a plurality of capacitors Cm and Cn provided in the semiconductor region AAC. Each of the capacitors Cm and Cn includes: a capacitor insulating film 42A on the semiconductor region AAC; capacitor electrodes 34Am and 34An on the capacitor insulating films 42A, respectively; and diffusion layers 32A adjacent to the capacitor electrodes 34Am and 34An. Each of wiring 29m and 29n connected to the capacitor electrodes 34Am and 34An is electrically separated per the capacitors Cm and Cn. Different potentials Vm and Vn are applied to the capacitor electrodes 34Am and 34An, respectively.
摘要翻译：要解决的问题：减少用于形成电容器的区域的占用面积。解决方案：半导体器件包括：设置在半导体衬底10中的半导体区域AAC; 以及设置在半导体区域AAC中的包括多个电容器Cm和Cn的电容器组。电容器Cm和Cn中的每一个包括：半导体区域AAC上的电容器绝缘膜42A; 电容器绝缘膜42A上的电容电极34Am和34An; 以及与电容器电极34Am和34An相邻的扩散层32A。连接到电容器电极34Am和34An的布线29m和29n中的每一个电容器Cm和Cn被电分离。不同的电位Vm和Vn分别施加到电容器电极34Am和34An。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2010165785A Semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2010165785A
公开(公告)日：2010-07-29
申请号：JP2009005778
申请日：2009-01-14
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKUDA KOICHI , NAKAMURA DAI , MATSUNAGA YASUHIKO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11519 , G11C16/0483 , H01L27/0207 , H01L27/11521 , H01L27/11526 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device and a method of manufacturing the same, wherein while interconnect resistance of each of a cell source line, a cell well line, and a power supply line is held low, hydrogen in a forming gas-annealing process can be supplied to a memory cell.
SOLUTION: The semiconductor memory device includes: a semiconductor substrate 11; a memory cell array MCA formed on the semiconductor substrate 11 and including a plurality of memory cells MC capable of electrically storing data; a sense amplifier S/A for detecting data stored in a memory cell; a source driver CSD electrically connected to a source side of the memory cell; a first interconnect CSL 3 for electrically connecting the source of the memory cell to the cell source driver; and a second interconnect VSSL3 formed in the same interconnect layer where the first interconnect is formed, insulated from the first interconnect, and electrically connected to the sense amplifier, wherein the first and second interconnects have a plurality of through holes H provided at predetermined intervals.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体存储器件及其制造方法，其中当电池源极线，电池管线和电源线中的每一个的互连电阻保持为低时，在可以向存储单元提供成形气体退火工艺。解决方案：半导体存储器件包括：半导体衬底11; 存储单元阵列MCA，其形成在半导体衬底11上并且包括能够电存储数据的多个存储单元MC; 用于检测存储在存储单元中的数据的读出放大器S / A; 源极驱动器CSD，电连接到存储单元的源极侧; 用于将存储器单元的源电连接到单元源驱动器的第一互连CSL 3; 以及第二互连VSSL3，其形成在与所述第一互连绝缘的所述第一互连的相同互连层中，并且电连接到所述读出放大器，其中所述第一和第二互连具有以预定间隔设置的多个通孔H. 版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2010123208A Nand flash memory 审中-公开
标题翻译： NAND闪存
公开(公告)号：JP2010123208A
公开(公告)日：2010-06-03
申请号：JP2008296841
申请日：2008-11-20
申请人： Toshiba Corp , 株式会社東芝
发明人： NAGAO TADASHI , WATANABE YOSHIHISA , FUKUDA KOICHI
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
CPC分类号： G11C16/08 , G11C16/16
摘要： PROBLEM TO BE SOLVED: To provide a NAND flash memory suppressing erroneous erasure of data in an unselected block. SOLUTION: The NAND flash memory, in which data is erased in blocks, has a plurality of memory cell transistors provided in each of the blocks, the memory cell transistor having a floating gate which is formed on a well formed on a semiconductor substrate via a first gate insulating film, and a control gate which is formed on the floating gate via a second gate insulating film being, and being capable of rewriting data by controlling the amount of charge accumulated on the floating gate; and a row decoder having a plurality of n-type transfer MOS transistors having drains connected to respective word lines each connected to the control gate of the corresponding memory cell transistor, the row decoder controlling the gate voltages and source voltages of the transfer MOS transistors. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种NAND闪存，其抑制未选择块中的数据的错误擦除。解决方案：以块为单位擦除数据的NAND闪存具有设置在每个块中的多个存储单元晶体管，存储单元晶体管具有形成在形成于半导体上的阱上的浮置栅极基板经由第一栅极绝缘膜，以及通过第二栅极绝缘膜形成在浮置栅极上的控制栅极，并且能够通过控制在浮动栅极上累积的电荷量来重写数据; 以及具有多个n型传输MOS晶体管的行解码器，其具有连接到各自字线的漏极，每个字线连接到相应的存储单元晶体管的控制栅极，行解码器控制转移MOS晶体管的栅极电压和源极电压。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2008108379A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2008108379A
公开(公告)日：2008-05-08
申请号：JP2006291404
申请日：2006-10-26
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMOSHITA MASAHIRO , HARA TAKAHIKO , FUKUDA KOICHI
IPC分类号： G11C16/06 , G01R31/28 , G11C16/02 , G11C29/04 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： H01L2224/48227 , H01L2224/73265 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing power consumption.
SOLUTION: The semiconductor integrated circuit device is equipped with: an internal power supply generating circuit; a semiconductor memory; a storage circuit 33 for recording the defective information of the semiconductor memory; and a control circuit 39 constituted so as to stop internal power generated from the internal power supply generating circuit when the defective information is read out.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够降低功耗的半导体集成电路。解决方案：半导体集成电路器件配备有内部电源发生电路; 半导体存储器用于记录半导体存储器的不良信息的存储电路33; 以及控制电路39，其构成为当读出缺陷信息时，停止从内部电源产生电路产生的内部电力。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2006294649A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006294649A
公开(公告)日：2006-10-26
申请号：JP2005109075
申请日：2005-04-05
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI MITSUHIRO , YOSHIKAWA SUSUMU , FUKUDA KOICHI
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/06 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , H01L27/0629 , H01L27/11526 , H01L27/11531
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of rationally achieving a resistor element having a high resistance and high resistance accuracy and a nonvolatile semiconductor storage element even if a design rule is reduced. SOLUTION: The semiconductor device is provided with a nonvolatile semiconductor storage element formed in a first semiconductor region provided on a semiconductor substrate; and a resistor element provided with a second semiconductor region provided on the semiconductor substrate, third insulating film formed on the second semiconductor region and having a thickness thicker than the that of the first insulating film, conductor layer formed with the same material as that of the first electrode on the third insulating film, second element isolation for separating the second semiconductor region, the third insulating film and the conductor layer like self alignment, fourth insulation film formed on the top surface of the conductor layer, and third and fourth electrodes formed on the fourth insulating films on both ends of the conductor layer, including the same material as that of at least one part of the second electrode and being connected to the conductor layer. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：即使设计规则减少，提供能够合理地实现具有高电阻和高电阻精度的电阻元件的半导体器件和非易失性半导体存储元件。解决方案：半导体器件设置有形成在设置在半导体衬底上的第一半导体区域中的非易失性半导体存储元件; 以及设置在半导体基板上的设置有第二半导体区域的电阻元件，形成在第二半导体区域上的厚度比第一绝缘膜厚的第三绝缘膜，与第一绝缘膜相同的材料形成的导体层第三绝缘膜上的第一电极，用于分离第二半导体区域的第二元件隔离，第三绝缘膜和导体层自对准，形成在导体层的顶表面上的第四绝缘膜，以及形成在第三绝缘膜上的第三和第四电极导体层两端的第四绝缘膜包括与第二电极的至少一部分相同的材料并连接到导体层。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006252641A Semiconductor memory device, and method of driving semiconductor memory device 有权
标题翻译：半导体存储器件以及驱动半导体存储器件的方法
公开(公告)号：JP2006252641A
公开(公告)日：2006-09-21
申请号：JP2005065949
申请日：2005-03-09
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKUDA KOICHI
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/30 , G11C16/16
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which is low in power consumption and current consumption and high in operation speed, and to provide a method of driving the semiconductor memory device. SOLUTION: The semiconductor memory device 10 is formed with: a semiconductor layer; a plurality of memory cells which is formed at the semiconductor layer and which can perform the write-in, erasure, or read-out of data based on voltages applied to a control electrode and the semiconductor layer; a first boosting circuit BCpgm for supplying voltage to the control electrode of a selected memory cell to which data are written; and a second boosting circuit BCpass for supplying a voltage to the electrode of a non-selection memory cell to which data are not to be written. When the data of the memory cell are erased, the potential of the semiconductor layer is boosted at a first boosting mode in which the boosting capability of the first boosting circuit is low and the boosting capability of the second boosting circuit is high, next, the potential of the semiconductor layer is boosted at a second boosting mode in which the boosting capability of the second boosting circuit is low and the boosting capability of the first boosting circuit is high. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种低功耗和电流消耗以及高操作速度的半导体存储器件，并提供一种驱动半导体存储器件的方法。解决方案：半导体存储器件10形成有：半导体层; 多个存储单元，其形成在所述半导体层处，并且可以基于施加到控制电极和所述半导体层的电压来执行数据的写入，擦除或读出; 用于向写入数据的所选存储单元的控制电极提供电压的第一升压电路BCpgm; 以及用于向不被写入数据的非选择存储单元的电极提供电压的第二升压电路BCpass。当存储单元的数据被擦除时，半导体层的电位以第一升压电路的升压能力低并且第二升压电路的升压能力高的第一升压模式升压，接下来，第二升压电路的升压能力低，第一升压电路的升压能力高的第二升压模式下升压半导体层的电位。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2006245547A Non-volatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：JP2006245547A
公开(公告)日：2006-09-14
申请号：JP2006011646
申请日：2006-01-19
申请人： Toshiba Corp , 株式会社東芝
发明人： ABE TAKUMI , FUKUDA KOICHI , MAEJIMA HIROSHI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory capable of reducing the wiring resistances of cell source lines and cell well lines without reducing integration degree. SOLUTION: Memory cell columns configured by arranging in a row direction a plurality of memory cell transistors and selective transistors that select the memory cell transistor, are disposed in a column, to constitute a memory array 30. A plurality of first cell well lines 21a, 21c, 21e are connected to well regions where a plurality of memory cell columns are formed. A plurality of first cell well lines 21a, 21c, 21e are electrically connected through a plurality of second cell well lines 22a to 22h in a wiring layer of the upper layer of the first well lines. A second cell source line 12 is connected to a source terminal of each selective transistor in a plurality of memory cell columns. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供能够降低单元源线和单元管线的布线电阻而不降低集成度的非易失性半导体存储器。解决方案：通过在行方向上配置多个存储单元晶体管和选择存储单元晶体管的选择晶体管配置的存储单元列被布置在列中，以构成存储器阵列30.多个第一单元阱线21a，21c，21e连接到形成有多个存储单元列的阱区域。多个第一单元阱管线21a，21c，21e通过第一阱管线的上层的布线层中的多个第二单元阱管线22a〜22h电连接。第二单元源极线12连接到多个存储单元列中每个选择晶体管的源极端子。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005353156A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2005353156A
公开(公告)日：2005-12-22
申请号：JP2004171583
申请日：2004-06-09
申请人： Toshiba Corp , 株式会社東芝
发明人： HOSONO KOJI , FUKUDA KOICHI
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C16/26 , G11C16/32 , G11C19/08
CPC分类号： G11C16/32 , G11C16/0483 , G11C16/26
摘要： PROBLEM TO BE SOLVED: To realize a stable memory core operation without being affected by variations in resistance. SOLUTION: A trimming is performed by measuring a clock signal CLK when a variable resistance circuit 72 in a clock signal generating circuit 70 is set to a prescribed resistance value on design and determining variation from the designed value of a resistance value. Trimming data is reflected to the trimming in a bit line control circuit 61. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：实现稳定的存储器核心操作而不受电阻变化的影响。解决方案：当时钟信号发生电路70中的可变电阻电路72在设计上被设置为规定的电阻值并且根据电阻值的设计值确定变化时，通过测量时钟信号CLK来进行修整。修剪数据被反映到位线控制电路61中的微调。版权所有：（C）2006，JPO＆NCIPI

9. 发明专利

JP2005235260A Nand type flash memory 有权
标题翻译： NAND型闪存
公开(公告)号：JP2005235260A
公开(公告)日：2005-09-02
申请号：JP2004040132
申请日：2004-02-17
申请人： Toshiba Corp , 株式会社東芝
发明人： ABE TAKUMI , MAEJIMA HIROSHI , FUKUDA KOICHI , HARA TAKAHIKO
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G11C11/5621 , G11C16/0483 , G11C2211/5641
摘要： PROBLEM TO BE SOLVED: To make a write property of a memory cell at an end part of a NAND column equivalent to that of a memory cell at a center part, and to reduce a pre-charge period of a bit line. SOLUTION: This flash memory is constituted so that each memory cell column connects 1st conducting paths of a plurality of nonvolatile memory cells in series, and is equipped with a memory cell array wherein the memory columns are arrayed in the matrix state, a plurality of 1st selection transistors respectively having a 2nd conducting path so that one end of the 2nd conducting path is connected to one end of the 1st conducting path, a plurality of bit lines connected to other ends of the 2nd conducting path, a plurality of 2nd selection transistors respectively having a 3rd conducting path so that one end of the 3rd conducting path is connected to other end of the 1st conducting path, and a source line connected to the other end of the 3rd conducting path, and at least one nonvolatile memory cell in the memory column is furnished with a function other than the external data storage function. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：使NAND列的端部的存储单元的写入特性等同于中心部分的存储单元的写入特性，并且减少位线的预充电周期。解决方案：该闪速存储器构成为使得每个存储单元列串联连接多个非易失性存储单元的第一导电路径，并且配备有存储单元阵列，其中存储器列以矩阵状排列，多个第一选择晶体管分别具有第二导电路径，使得第二导电路径的一端连接到第一导电路径的一端，连接到第二导电路径的另一端的多个位线，多个第二导电路径选择晶体管分别具有第三导电路径，使得第三导电路径的一端连接到第一导电路径的另一端，以及连接到第三导电路径的另一端的源极线以及至少一个非易失性存储单元在内存列中配置了外部数据存储功能以外的功能。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2005190533A Semiconductor device and driving method of the device 有权
标题翻译：设备的半导体器件和驱动方法
公开(公告)号：JP2005190533A
公开(公告)日：2005-07-14
申请号：JP2003429147
申请日：2003-12-25
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKUDA KOICHI , IMAMIYA KENICHI
IPC分类号： G11C16/06 , G05F1/10 , G11C7/00 , G11C11/40 , H02M3/07
CPC分类号： H02M3/073
摘要： PROBLEM TO BE SOLVED: To provide a boosting circuit semiconductor device in which overshoots and ripples in the output potential of a boosting circuit are reduced compared with a conventional boosting circuit without increasing a clock generating circuit and the output potential of the boosting circuit is maintained in the vicinity of a desired potential. SOLUTION: A semiconductor device 100 is provided with a clock generating circuit 111 which generates clock signals, a boosting circuit 112 which boosts a supply voltage using the clock signals and outputs the boosted supply voltage, a potential detecting circuit 114 which detects the output potential of the boosting circuit 112 and outputs frequency switching signals having logic dependent on the output potential and a frequency switching circuit 120 which is located between the clock generating circuit 111 and the boosting circuit 112 and changes the frequency of the clock signals from the clock generating circuit 111 to the boosting circuit 112 based on the frequency switching signals. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种升压电路半导体器件，其中与常规升压电路相比，升压电路的输出电位中的过冲和波纹减小而不增加时钟产生电路和升压电路的输出电位保持在所需电位附近。解决方案：半导体器件100设置有产生时钟信号的时钟发生电路111，升压电路112，其使用时钟信号升高电源电压并输出升压的电源电压;电位检测电路114，其检测升压电路112的输出电位，并输出具有取决于输出电位的逻辑的频率切换信号，以及位于时钟发生电路111和升压电路112之间的频率切换电路120，并且将时钟信号的频率从时钟基于频率切换信号将发生电路111发送到升压电路112。版权所有（C）2005，JPO＆NCIPI

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