专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2012038818A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012038818A
公开(公告)日：2012-02-23
申请号：JP2010175693
申请日：2010-08-04
申请人： Toshiba Corp , 株式会社東芝
发明人： KUTSUKAKE HIROYUKI , KATO TOKO , FUKUDA KOICHI , WATANABE YOSHIHISA , MASUDA KAZUNORI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H02M3/07
CPC分类号： H01L27/11526 , H01L27/11521 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To reduce the occupied area of the region for forming capacitors.SOLUTION: A semiconductor device comprises: a semiconductor region AAC provided in a semiconductor substrate 10; and a capacitor group including a plurality of capacitors Cm and Cn provided in the semiconductor region AAC. Each of the capacitors Cm and Cn includes: a capacitor insulating film 42A on the semiconductor region AAC; capacitor electrodes 34Am and 34An on the capacitor insulating films 42A, respectively; and diffusion layers 32A adjacent to the capacitor electrodes 34Am and 34An. Each of wiring 29m and 29n connected to the capacitor electrodes 34Am and 34An is electrically separated per the capacitors Cm and Cn. Different potentials Vm and Vn are applied to the capacitor electrodes 34Am and 34An, respectively.
摘要翻译：要解决的问题：减少用于形成电容器的区域的占用面积。解决方案：半导体器件包括：设置在半导体衬底10中的半导体区域AAC; 以及设置在半导体区域AAC中的包括多个电容器Cm和Cn的电容器组。电容器Cm和Cn中的每一个包括：半导体区域AAC上的电容器绝缘膜42A; 电容器绝缘膜42A上的电容电极34Am和34An; 以及与电容器电极34Am和34An相邻的扩散层32A。连接到电容器电极34Am和34An的布线29m和29n中的每一个电容器Cm和Cn被电分离。不同的电位Vm和Vn分别施加到电容器电极34Am和34An。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2008004175A Nonvolatile semiconductor memory device and its voltage applying method 审中-公开
标题翻译：非易失性半导体存储器件及其电压应用方法
公开(公告)号：JP2008004175A
公开(公告)日：2008-01-10
申请号：JP2006173127
申请日：2006-06-22
申请人： Toshiba Corp , Toshiba Information Systems (Japan) Corp , 東芝情報システム株式会社 , 株式会社東芝
发明人： SAKO MARIO , UMEZAWA AKIRA , HARA NORIMASA , MASUDA KAZUNORI , HASE EMIKO
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To achieve simultaneously micronization and capacity increase, and improvement of read-out margin in a nonvolatile semiconductor device. SOLUTION: The nonvolatile semiconductor memory device is provided with a plurality of nonvolatile memory cells 114 arranged in a matrix state, source lines SL connected to sources of the nonvolatile memory cells, a source line drive transistor 121 comprising of a high voltage transistor connected to this source line during erasion, a plurality of bit lines BL connected respectively to drains of a plurality of nonvolatile memory cells arranged for each column, and a column selecting circuit selecting a bit line and constituted of a plurality of column selecting transistors Q0 to Qm of which the breakdown strength between the source and the drain is lower than the high voltage transistor. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：同时实现微粉化和容量增加，并提高非易失性半导体器件中的读出余量。解决方案：非易失性半导体存储器件设置有以矩阵状排列的多个非易失性存储单元114，连接到非易失性存储单元的源极的源极线SL，包括高压晶体管的源极线驱动晶体管121 在擦除期间与该源极线连接的多个位线BL分别连接到为每列配置的多个非易失性存储单元的漏极，列选择电路选择位线并由多个列选择晶体管Q0至其源极和漏极之间的击穿强度低于高压晶体管的Qm。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2014187183A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014187183A
公开(公告)日：2014-10-02
申请号：JP2013061083
申请日：2013-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI NORIHISA , TAKAHASHI TSUTOMU , MASUDA KAZUNORI , HATAKEYAMA KAZUO
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/8247 , H01L23/522 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that is highly reliable.SOLUTION: A semiconductor device according to an embodiment comprises: a first-conductivity-type semiconductor layer having a first surface and a second surface opposite to the first surface; a conductive layer penetrating the semiconductor layer from the first surface side to the second surface side; a first-conductivity-type first semiconductor region which surrounds a part of the conductive layer, and of which the portion other than a front surface is surrounded by the semiconductor layer on the second surface side of the semiconductor layer; and a first insulating film provided between the conductive layer and the semiconductor layer and between the conductive layer and the first semiconductor region. The density of first-conductivity-type impurities contained in the first semiconductor region is higher than the density of first-conductivity-type impurities contained in the semiconductor layer.
摘要翻译：要解决的问题：提供高可靠性的半导体器件。解决方案：根据实施例的半导体器件包括：第一导电型半导体层，具有与第一表面相对的第一表面和第二表面; 从所述第一表面侧到所述第二表面侧穿透所述半导体层的导电层; 第一导电型第一半导体区域，其围绕导电层的一部分，并且其前表面以外的部分被半导体层的第二表面侧上的半导体层包围; 以及设置在所述导电层和所述半导体层之间以及所述导电层和所述第一半导体区域之间的第一绝缘膜。包含在第一半导体区域中的第一导电型杂质的密度高于包含在半导体层中的第一导电型杂质的密度。

4. 发明专利

JP2010021496A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010021496A
公开(公告)日：2010-01-28
申请号：JP2008183210
申请日：2008-07-14
申请人： Toshiba Corp , 株式会社東芝
发明人： MASUDA KAZUNORI
IPC分类号： H01L21/336 , H01L21/28 , H01L21/283 , H01L21/768 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42324 , H01L29/6656
摘要： PROBLEM TO BE SOLVED: To provide a compact semiconductor device which can be formed without deteriorating the characteristics of a transistor, and to provide the method of manufacturing the same. SOLUTION: The semiconductor device includes: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate through the gate insulating film; a first silicon nitride film formed on the upper surface of the gate electrode; a protection insulating film formed on the side face of the gate electrode; a second silicon nitride film formed on the side face of the protection insulating film; and a third silicon nitride film formed on the upper surface of the protection insulating film and having a bottom formed upper than the bottom of the first silicon nitride film. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供可以形成的小型半导体器件，而不会降低晶体管的特性，并提供其制造方法。解决方案：半导体器件包括：半导体衬底; 形成在半导体衬底上的栅极绝缘膜; 通过所述栅极绝缘膜形成在所述半导体衬底上的栅电极; 形成在所述栅电极的上表面上的第一氮化硅膜; 形成在栅电极的侧面上的保护绝缘膜; 形成在所述保护绝缘膜的侧面上的第二氮化硅膜; 以及形成在所述保护绝缘膜的上表面上并具有形成在所述第一氮化硅膜的底部以上的底部的第三氮化硅膜。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2012059776A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2012059776A
公开(公告)日：2012-03-22
申请号：JP2010199105
申请日：2010-09-06
申请人： Toshiba Corp , 株式会社東芝
发明人： HATANO TOMOAKI , ARAI NORIHISA , MASUDA KAZUNORI
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method that can assure accurate ion implantation to a high breakdown voltage transistor without increasing the number of processes.SOLUTION: The semiconductor device manufacturing method comprises the steps of: removing, in a first element formation region (AA1), a first portion (H1') of a mask material (M1) located immediately above a first region (R1') on which a gate electrode of a first transistor (Tr1) is to be formed while leaving the mask material (M1) on the frist element formation region (AA1) at a region except the first region (H1'); and forming an opening of the mask material (M1) by removing, in a second element formation region (AA2), at least a second portion (H1) of the mask material (M1) located immediately above a second region (R1) on which a gate electrode of a second transistor (Tr2) is to be formed and at least third portions (H2, H3) of the mask material (M1) respectively located immediately above third regions (R2, R3) on which source/drain diffusion regions of the second transistor (Tr2) are to be formed.
摘要翻译：要解决的问题：提供一种半导体制造方法，其可以确保精确的离子注入到高耐压晶体管，而不增加工艺数量。解决方案：半导体器件制造方法包括以下步骤：在第一元件形成区域（AA1）中去除位于第一区域（R1'）正上方的掩模材料（M1）的第一部分（H1'），），在除了第一区域（H1'）之外的区域在第一元件形成区域（AA1）上留下掩模材料（M1）时，要形成第一晶体管（Tr1）的栅电极; 以及通过在第二元件形成区域（AA2）中除去位于第二区域（R1）正上方的掩模材料（M1）的至少第二部分（H1），形成掩模材料（M1）的开口，在第二区域形成第二晶体管（Tr2）的栅电极，并且掩模材料（M1）的至少第三部分（H2，H3）分别位于第三区（R2，R3）的正上方，第三区（R2，R3）的源极/漏极扩散区将形成第二晶体管（Tr2）。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2011014838A Non-volatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011014838A
公开(公告)日：2011-01-20
申请号：JP2009159975
申请日：2009-07-06
申请人： Toshiba Corp , 株式会社東芝
发明人： MASUDA KAZUNORI , NARUGE KIYOMI , MORIKADO MUTSUO
IPC分类号： H01L29/792 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor non-volatile memory device which suppresses deterioration of resistance to leakage associated with the microfabrication of memory cells by reducing a leakage current occurring in an inter-electrode insulating film between the control gate and the floating gate.SOLUTION: In a non-volatile semiconductor memory device which integrates a plurality of non-volatile memory cells on a semiconductor substrate 1, each memory cell includes a tunnel insulating film 2a formed on the semiconductor substrate 1, a floating gate electrode 3a formed on the tunnel insulating film 2a, a first inter-electrode insulating film 4a formed on the upper surface of the floating gate electrode 3a, a second inter-electrode insulating film 5a formed so as to cover the side surface of the floating gate electrode 3a and the first inter-electrode insulating film 4a, and a control electrode 6a formed on the second inter-electrode film 5a.
摘要翻译：要解决的问题：提供一种半导体非易失性存储器件，其通过减少在控制栅极和浮置栅极之间的电极间绝缘膜中产生的漏电流来抑制与微存储单元的微细加工相关的漏电性的劣化。解决方案：在半导体衬底1上集成多个非易失性存储单元的非易失性半导体存储器件中，每个存储单元包括形成在半导体衬底1上的隧道绝缘膜2a，形成在半导体衬底1上的浮栅电极3a 隧道绝缘膜2a，形成在浮栅电极3a的上表面上的第一电极间绝缘膜4a，形成为覆盖浮栅电极3a的侧表面的第二电极间绝缘膜5a和第一电极间绝缘膜4a和形成在第二电极间膜5a上的控制电极6a。

7. 发明专利

JPH1074832A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH1074832A
公开(公告)日：1998-03-17
申请号：JP22825696
申请日：1996-08-29
申请人： TOSHIBA CORP
发明人： MASUDA KAZUNORI
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/768 , H01L21/8247 , H01L23/522 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To solve problem such as the generation of short mode when a contact hole approaches element separating areas, without taking allowance between the contact hole and element separating areas by providing etching barrier layers which are self-aligned with the side walls of the elementseparating areas above the element-separating areas. SOLUTION: Trenches corresponding to element-separating area patterns are formed into a semiconductor substrate 1, and an insulator which constitutes element separating areas 2 is buried in the trenches. Then etching barrier layers which contain insulating films 5, containing a material which is different from the insulator of the areas 2 and self-aligned with the side wall of the area 2, are provided above the areas 2. For example, the areas 2 which are composed of silicon dioxide and protruded from the surface of the substrate 1 are formed on the substrate 1 and the silicon nitride films 5 are formed in the areas 2, except the forming areas of control gates 14. In addition, side-wall nitride films 7 are formed on the side walls of the projecting sections of the area 2 and the nitride films 5.

8. 发明专利

JP2002118177A SEMICONDUCTOR DEVICE AND ITS FABRICATING METHOD 失效
公开(公告)号：JP2002118177A
公开(公告)日：2002-04-19
申请号：JP2000310155
申请日：2000-10-11
申请人： TOSHIBA CORP
发明人： WATABE HIROSHI , NARUGE KIYOMI , MASUDA KAZUNORI
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/8247 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a high integration semiconductor device in which breakdown strength of a high breakdown strength PMOS transistor is ensured. SOLUTION: The semiconductor device comprises an N type transistor 4 having a first gate 18, an N type lightly doped diffusion layer 36 formed around the first gate, an N type heavily doped diffusion layer 6 formed around the N type lightly doped diffusion layer, and first gate sidewalls 29, 47 and 82 formed around the first gate, and a P type transistor 3 having a second gate 13, a P type lightly doped diffusion layer 35 formed around the second gate, a P type heavily doped diffusion layer 11 formed around the P type lightly doped diffusion layer, and second gate sidewalls 10, 29 and 82 formed around the gate wherein the P type lightly doped diffusion layer extends farther downward of the second gate than the N type lightly doped diffusion layer extending downward of the first gate.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式