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1. 发明专利

JP2010123211A Write method in semiconductor memory device 审中-公开
标题翻译：半导体存储器件中的写入方法
公开(公告)号：JP2010123211A
公开(公告)日：2010-06-03
申请号：JP2008296865
申请日：2008-11-20
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE YOSHIHISA
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C16/3454 , G11C11/5628 , G11C16/0483 , G11C16/24 , G11C16/3459 , G11C2211/5621
摘要： PROBLEM TO BE SOLVED: To shorten a data write operation time, in a NAND type flash memory adopting a write method which needs two data write operations. SOLUTION: For example, when writing final data at a desired threshold voltage level in a nonvolatile memory cell, first, a preliminary data write operation of writing preliminary data of a temporary level lower than the desired threshold voltage level, is performed. Then, write verify read of the preliminary data write is performed. A WL waiting WTa of the verify read is made shorter than it (WL waiting time WT) of write verify read of the final data. After that, final data write operation of writing final data of the desired threshold voltage level is performed, and write verify read of final data write is performed. A WL waiting time WT at this time is made a time in which a potential is sufficiently stabilized so that difference of voltage levels between the root and the top end of a selected word line is not caused. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：在采用需要两个数据写入操作的写入方法的NAND型闪速存储器中，缩短数据写入操作时间。解决方案：例如，当在非易失性存储单元中写入期望的阈值电压电平的最终数据时，首先，执行写入低于期望阈值电压电平的临时电平的初步数据的初步数据写入操作。然后，执行初步数据写入的写入验证读取。验证读取的WL等待WTa比其最终数据的写入验证读取（WL等待时间WT）短。之后，执行写入期望阈值电压电平的最终数据的最终数据写入操作，并且执行最终数据写入的写入验证读取。此时的WL等待时间WT成为电位足够稳定的时间，从而不会引起所选字线的根和顶端之间的电压电平的差异。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2005353760A Semiconductor integrated circuit, boosting circuit and capacitor 有权
标题翻译：半导体集成电路，升压电路和电容器
公开(公告)号：JP2005353760A
公开(公告)日：2005-12-22
申请号：JP2004171584
申请日：2004-06-09
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE YOSHIHISA
IPC分类号： G11C16/06 , G11C16/04 , G11C16/08 , G11C16/30 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/94
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/08 , H01L27/115 , H01L29/94
摘要： PROBLEM TO BE SOLVED: To prevent the deterioration of characteristics due to a parasitic capacity generated in the surroundings of a capacitor. SOLUTION: The capacitor 532 of a boosting circuit is constituted of a well capacitor. Further, a part of a first wiring layer 26 for impressing a voltage on the n-type well 21 of the well capacitor is formed so as to cover the upper part of a gate electrode 23. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止由于在电容器的周围产生的寄生电容引起的特性劣化。解决方案：升压电路的电容器532由阱电容器构成。此外，形成用于在阱电容器的n型阱21上施加电压的第一布线层26的一部分，以覆盖栅电极23的上部。（C）2006， JPO＆NCIPI

3. 发明专利

JP2010073245A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2010073245A
公开(公告)日：2010-04-02
申请号：JP2008238092
申请日：2008-09-17
申请人： Toshiba Corp , 株式会社東芝
发明人： FURUTA YUKA , WATANABE YOSHIHISA
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/26 , G11C16/0483
摘要： PROBLEM TO BE SOLVED: To provide a NAND type flash memory that reduces current consumption. SOLUTION: This is a method of controlling a NAND type flash memory provided with a latch circuit temporarily holding data. First current consumption of the latch circuit is measured in a first state in which first logic is held in the latch circuit. Second current consumption of the latch circuit is measured in a second state in which second logic obtained by inverting the first logic is held in the latch circuit. The first current consumption is compared with the second current consumption. The logic corresponding to a state in which the current value is smaller is held in the latch circuit. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种降低电流消耗的NAND型闪存。解决方案：这是一种控制配置有临时保存数据的锁存电路的NAND型闪速存储器的方法。在锁存电路中保持第一逻辑的第一状态下测量锁存电路的第一电流消耗。在第二状态下测量锁存电路的第二电流消耗，其中通过将第一逻辑反相获得的第二逻辑保持在锁存电路中。将第一次电流消耗与第二次电流消耗进行比较。与当前值较小的状态相对应的逻辑保持在锁存电路中。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2011070717A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011070717A
公开(公告)日：2011-04-07
申请号：JP2009219089
申请日：2009-09-24
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE YOSHIHISA
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory in which the number of writing pulses to be applied is lessened and improvement in the speed of data writing is enabled. SOLUTION: The nonvolatile semiconductor memory device is equipped with: a memory cell array including a plurality of memory cells to store N value data (N being an integer equal to or larger than 3); and a writing circuit configured to repeatedly execute a writing cycle on a plurality of memory cells until data writing is finished. The writing circuit divides the pulse width of the writing pulse into a plurality of sections to change the pulse height among the sections to provide voltages for writing to different target threshold levels, and brings the bit line connected with the memory cell in which writing to the respective target threshold levels is performed, into a writable selected state by synchronizing it with the applying period to the respective target threshold level. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种非易失性半导体存储器，其中要施加的写入脉冲的数量减少，并且能够提高数据写入的速度。解决方案：非易失性半导体存储器件配备有：存储单元阵列，包括存储N个值数据的多个存储器单元（N是等于或大于3的整数）; 以及写入电路，被配置为在数据写入结束之前重复地执行多个存储单元上的写入周期。写入电路将写入脉冲的脉冲宽度分割为多个部分，以改变各部分之间的脉冲高度，以提供用于写入不同目标阈值电平的电压，并且将与其写入的存储器单元连接的位线通过将相应的目标阈值水平与施加周期同步到相应的目标阈值水平来执行各个目标阈值水平为可写入选择状态。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2010211899A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2010211899A
公开(公告)日：2010-09-24
申请号：JP2009059732
申请日：2009-03-12
申请人： Toshiba Corp , 株式会社東芝
发明人： OGAWA TAKESHI , WATANABE YOSHIHISA
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C16/06 , G11C16/32 , G11C16/3418
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which improves the reliability of operation. SOLUTION: The semiconductor storage device includes memory cells MT which store data; bit lines BL and source lines SL each of which is electrically connected to the memory cells MT; a source line driver 20 which applies voltages to the source lines SL; a sense amplifier 12 which senses currents to read out the data; a counting circuit 23 which counts the number of the memory cells MT, which are in an "On" or/and "Off" state(s), when a read-out operation or a verification operation is conducted; a detection circuit 21, which detects whether the voltages of the source lines SL exceed reference voltages VREF_SRC, when the read-out operation or the verification operation is conducted; and a control circuit 16 which controls the number of times that the sensing is made in the sense amplifier 12, according to the result of the detection in the detection circuit 21, and also controls the driving force of the source line driver 20, according to the result of the counting performed in the counting circuit 23. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供提高操作可靠性的半导体存储装置。解决方案：半导体存储装置包括存储数据的存储单元MT; 位线BL和源极线SL，其各自电连接到存储单元MT; 源极线驱动器20，其向源极线SL施加电压; 感测放大器12，其感测电流以读出数据; 计数电路23，其在进行读出操作或验证操作时对存在“On”或/或“Off”状态的存储单元MT的数量进行计数; 检测电路21，其在进行读出操作或验证操作时检测源极线SL的电压是否超过参考电压VREF_SRC; 根据检测电路21的检测结果，根据检测电路21的检测结果，控制检测放大器12进行检测次数的控制电路16，根据检测电路21的检测结果控制源极线驱动器20的驱动力。在计数电路23中进行计数的结果。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2010160866A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2010160866A
公开(公告)日：2010-07-22
申请号：JP2009003860
申请日：2009-01-09
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE YOSHIHISA
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C16/10
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which transfer voltage to a word line can be compensated even when a property of a drive transistor of a word line is deteriorated. SOLUTION: A voltage generating circuit 91 generates first voltage being higher than write-in voltage during write-in and generates erasing voltage during erasure. In a first transistor Tr_LIM, first voltage generated by the voltage generating circuit is supplied to one end of a current path and a gate, and write-in voltage is output from the other end of the current path. In a drive transistor Tr_0, Tr_1, Tr_2, ..., one end of the current path is connected to the word line, the first voltage is supplied to the gate, and the write-in voltage is supplied to the other end of the current path. A stress apply means 96 supplies erasure voltage to the other end of the current path of the first transistor during erasure. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储器件，其中即使当字线的驱动晶体管的特性劣化时，也可以补偿对字线的转印电压。解决方案：电压产生电路91在写入期间产生高于写入电压的第一电压，并且在擦除期间产生擦除电压。在第一晶体管Tr_LIM中，由电压产生电路产生的第一电压被提供给电流路径和栅极的一端，并且从当前路径的另一端输出写入电压。在驱动晶体管Tr_0，Tr_1，Tr_2，...中，电流路径的一端连接到字线，第一电压被提供给栅极，并且写入电压被提供给当前路径。应力施加装置96在擦除期间向第一晶体管的电流路径的另一端提供擦除电压。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2008052808A Nonvolatile semiconductor memory device and method of reading data, and memory card 审中-公开
标题翻译：非易失性半导体存储器件和读取数据的方法以及存储卡
公开(公告)号：JP2008052808A
公开(公告)日：2008-03-06
申请号：JP2006227254
申请日：2006-08-24
申请人： Toshiba Corp , 株式会社東芝
发明人： IWAI MAKOTO , WATANABE YOSHIHISA
IPC分类号： G11C16/04 , G11C16/02
CPC分类号： G11C16/3418 , G11C16/3427
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device achieving high reliability and high speed read-out, and a method of reading data, and a memory card mounted with the nonvolatile semiconductor memory device. SOLUTION: The device includes a memory cell array having a plurality of NAND memory cell units including a plurality of memory cells and first and second selection transistors, a plurality of word lines and a plurality of bit lines, and a data read-out controller. The data read-out controller applies the read pass voltage to the non-selection memory cell other than the selection memory cell, when selecting one of the memory cells and reading out the data, then boosts the voltage applied to a control gate of the first and second selection transistors and, lowers the read pass voltage of the word line to be applied to the first and second selection transistors relating to the step-up and at least one to the adjacent non-selection memory cell than the read pass voltage of the word line to be applied to the other non-selection memory cell. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供实现高可靠性和高速读出的非易失性半导体存储器件以及读取数据的方法以及安装有非易失性半导体存储器件的存储卡。解决方案：该器件包括具有多个NAND存储器单元单元的存储单元阵列，该存储单元阵列包括多个存储单元和第一和第二选择晶体管，多个字线和多个位线，输出控制器。数据读出控制器在选择存储单元之一并读取数据之后，将读通过电压施加到除选择存储单元以外的非选择存储单元，然后升压施加到第一和第二选择晶体管，并且降低要施加到与升压相关的第一和第二选择晶体管的字线的读取通过电压，并且降低与相邻非选择存储器单元的读取通过电压相比的至少一个的读取通过电压要应用于其他非选择存储单元的字线。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007133999A Nonvolatile semiconductor memory device and memory card mounting the same 有权
标题翻译：非易失性半导体存储器件和存储卡安装相同
公开(公告)号：JP2007133999A
公开(公告)日：2007-05-31
申请号：JP2005327725
申请日：2005-11-11
申请人： Toshiba Corp , 株式会社東芝
发明人： IWAI MAKOTO , WATANABE YOSHIHISA
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which coupling noise is reduced further when data are read and whose reliability is high. SOLUTION: When data of a memory cell adjacent to a drain side selection transistor is read, a source side selection gate is boosted after a drain side selection gate line is boosted. When data of a memory cell adjacent to a source side selection transistor is read, the drain side selection gate line is boosted after the source side selection gate line is boosted. Voltage applied to word lines of the memory cell adjacent to the drain side selection transistor or the memory cell adjacent to the source side selection transistor is different between the case where a source side selection gate is boosted after a drain side selection gate line is boosted, and the case where a drain side selection gate is boosted after a source side selection gate line is boosted. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种非易失性半导体存储器件，其中当读取数据并且其可靠性高时，耦合噪声进一步降低。解决方案：当读取与漏极侧选择晶体管相邻的存储单元的数据时，在漏极侧选择栅极线被升压之后，源极侧选择栅极被升压。当读取与源极侧选择晶体管相邻的存储单元的数据时，在对源极侧选择栅极线进行升压之后，对漏极侧选择栅极线进行升压。施加到与漏极侧选择晶体管或与源极侧选择晶体管相邻的存储单元相邻的存储单元的字线的电压在漏极侧选择栅极线被升压之后提高源极侧选择栅极的情况是不同的，并且在源极侧选择栅极线被提升之后，漏极侧选择栅极被升压的情况。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2012038818A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012038818A
公开(公告)日：2012-02-23
申请号：JP2010175693
申请日：2010-08-04
申请人： Toshiba Corp , 株式会社東芝
发明人： KUTSUKAKE HIROYUKI , KATO TOKO , FUKUDA KOICHI , WATANABE YOSHIHISA , MASUDA KAZUNORI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H02M3/07
CPC分类号： H01L27/11526 , H01L27/11521 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To reduce the occupied area of the region for forming capacitors.SOLUTION: A semiconductor device comprises: a semiconductor region AAC provided in a semiconductor substrate 10; and a capacitor group including a plurality of capacitors Cm and Cn provided in the semiconductor region AAC. Each of the capacitors Cm and Cn includes: a capacitor insulating film 42A on the semiconductor region AAC; capacitor electrodes 34Am and 34An on the capacitor insulating films 42A, respectively; and diffusion layers 32A adjacent to the capacitor electrodes 34Am and 34An. Each of wiring 29m and 29n connected to the capacitor electrodes 34Am and 34An is electrically separated per the capacitors Cm and Cn. Different potentials Vm and Vn are applied to the capacitor electrodes 34Am and 34An, respectively.
摘要翻译：要解决的问题：减少用于形成电容器的区域的占用面积。解决方案：半导体器件包括：设置在半导体衬底10中的半导体区域AAC; 以及设置在半导体区域AAC中的包括多个电容器Cm和Cn的电容器组。电容器Cm和Cn中的每一个包括：半导体区域AAC上的电容器绝缘膜42A; 电容器绝缘膜42A上的电容电极34Am和34An; 以及与电容器电极34Am和34An相邻的扩散层32A。连接到电容器电极34Am和34An的布线29m和29n中的每一个电容器Cm和Cn被电分离。不同的电位Vm和Vn分别施加到电容器电极34Am和34An。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2010123208A Nand flash memory 审中-公开
标题翻译： NAND闪存
公开(公告)号：JP2010123208A
公开(公告)日：2010-06-03
申请号：JP2008296841
申请日：2008-11-20
申请人： Toshiba Corp , 株式会社東芝
发明人： NAGAO TADASHI , WATANABE YOSHIHISA , FUKUDA KOICHI
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
CPC分类号： G11C16/08 , G11C16/16
摘要： PROBLEM TO BE SOLVED: To provide a NAND flash memory suppressing erroneous erasure of data in an unselected block. SOLUTION: The NAND flash memory, in which data is erased in blocks, has a plurality of memory cell transistors provided in each of the blocks, the memory cell transistor having a floating gate which is formed on a well formed on a semiconductor substrate via a first gate insulating film, and a control gate which is formed on the floating gate via a second gate insulating film being, and being capable of rewriting data by controlling the amount of charge accumulated on the floating gate; and a row decoder having a plurality of n-type transfer MOS transistors having drains connected to respective word lines each connected to the control gate of the corresponding memory cell transistor, the row decoder controlling the gate voltages and source voltages of the transfer MOS transistors. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种NAND闪存，其抑制未选择块中的数据的错误擦除。解决方案：以块为单位擦除数据的NAND闪存具有设置在每个块中的多个存储单元晶体管，存储单元晶体管具有形成在形成于半导体上的阱上的浮置栅极基板经由第一栅极绝缘膜，以及通过第二栅极绝缘膜形成在浮置栅极上的控制栅极，并且能够通过控制在浮动栅极上累积的电荷量来重写数据; 以及具有多个n型传输MOS晶体管的行解码器，其具有连接到各自字线的漏极，每个字线连接到相应的存储单元晶体管的控制栅极，行解码器控制转移MOS晶体管的栅极电压和源极电压。版权所有（C）2010，JPO＆INPIT

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