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1. 发明专利

JPS62200757A MOS-TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62200757A
公开(公告)日：1987-09-04
申请号：JP4375186
申请日：1986-02-28
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： ATSUMI SHIGERU , SAITO SHINJI , TANAKA SUMIO , OTSUKA NOBUAKI , YOSHIKAWA KUNIYOSHI , KAMEI TAKASHI
IPC分类号： H01L21/8234 , G11C11/419 , H01L21/8238 , H01L21/8247 , H01L27/088 , H01L27/092 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To prevent the occurrence of nonuniformity in electric characteristics between transistors in a plurality by a construction wherein a low-concentration diffused region of a drain region of a transistor having an LDD structure is provided in two places for one transistor. CONSTITUTION:First to third semiconductor regions 12-14, which are formed by diffusion of impurities of a second conductivity type, isolated from one another and arranged in a row, are provided on a semiconductor substrate 11 of a first conductivity type, and first and second gate electrodes 17 are provided on the substrate 11 between the first and second semiconductor regions 12 and 13 and between the second and third semiconductor regions 13 and 14, while means 20 to connect electrically the first and third semiconductor regions 12 and 14 and means to connect electrically the first and second gate electrodes 17 are provided. Moreover, fourth and fifth semiconductor regions 18 and 19 wherein impurities of the second conductivity type are diffused in lower concentration than in the first and third semiconductor regions 12 and 14 are provided on the gate electrode 17 side of the first semiconductor region 12 and the third semiconductor region 14, respectively. The first, third, fourth and fifth semiconductor regions 12, 14, 18 and 19 are formed as drain regions, and the second semiconductor region 13 as a source region.

2. 发明专利

JPS62175999A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS62175999A
公开(公告)日：1987-08-01
申请号：JP1721186
申请日：1986-01-29
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： TANAKA SUMIO , ATSUMI SHIGERU , OTSUKA NOBUAKI , KAMEI TAKASHI
IPC分类号： H01L27/10 , G11C16/06 , G11C17/00 , H01L21/8247 , H01L29/78 , H01L29/788 , H01L29/792 , H03K19/0185
摘要： PURPOSE:To shorten a pitch of a line decoder, and to realize a high integration of a memory cell by providing the first and the second potential selecting means for selecting one of the first and the second potentials and outputting it to the respective nodes, and an amplifying circuit of a complementary MOS type. CONSTITUTION:In case of executing write of a data to a memory cell 40, a potential VPP of +12V is supplied to a gate of a MOS transistor 13 in a potential selecting circuit 15, and a gate of a MOS transistor 19 in a potential selecting circuit 21, respectively, and both these transistors 13 and 19 are set to an on-state. Subsequently, the potential VPP of +12V is outputted to a node 16 and 22, respectively, and also, since a MOS transistor 18 is set to an on-state, the potential VPP of +12V which has been outputted to the node 16 is outputted to a node 17. At this case, in case the corresponding line wire 36 has been selected, a signal potential of a node 33 drops to about '0'V. Also, a P channel MOS transistor 37 in a CMOS inverter 39 becomes an on-state, and the potential of the line wire 36 is set to +12V of the potential of the node 22.

3. 发明专利

JPS63293800A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS63293800A
公开(公告)日：1988-11-30
申请号：JP13080587
申请日：1987-05-27
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： IMAMIYA KENICHI , TANAKA SUMIO , MIYAMOTO JUNICHI , ATSUMI SHIGERU , OTSUKA NOBUAKI , IYAMA YUMIKO
IPC分类号： G11C29/00 , G11C16/02 , G11C16/06 , G11C16/34 , G11C17/00 , G11C29/12
摘要： PURPOSE:To secure a sufficient power supply margin by means of all access operation including normal reading operation by providing the titled memory with a circuit for changing a data reading reference in a reading mode and a program verify mode. CONSTITUTION:At the time of the program verify mode, a dummy cell 11 capable of applying earth potential to its gate is turned off and a reference potential generated at that time is expressed by V2. At the time normal reading, potential Vcc is applied to the gate of the dummy cell 11, the dummy cell 11 is turned on and generates a reference voltage shown by V1, then V1

4. 发明专利

JPS62231500A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS62231500A
公开(公告)日：1987-10-12
申请号：JP7300286
申请日：1986-03-31
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： ATSUMI SHIGERU , TANAKA SUMIO , OTSUKA NOBUAKI , KAMEI TAKASHI
IPC分类号： G11C17/00 , G11C7/06 , G11C16/12 , G11C16/28 , G11C16/34 , G11C29/00 , G11C29/12
摘要： PURPOSE:To monitor the shift quantity of a threshold voltage of a memory cell accurately and to a sufficiently large value by connecting a control gate of a memory cell and a gate of a MOS transistor (TR) selecting a memory cell and a dummy cell to a high potential terminal in using an internal test circuit. CONSTITUTION:A high potential Vpp is applied to a work line WL and a Y selection BL at write, a power voltage Vcc is applied at read and gates of a memory cell 22 and MOS TRs 23, 31 are connected to a high potential Vpp in using the internal test circuit. In this case, a potential rising gradually is given to the high potential Vpp terminal externally to read the Vpp when the data is changed from the write state into the non-write state, the shift quantity(write quantity) DELTAVTH is recognized withstanding a high potential, the value of the shift quantity DELTAVTH for evaluation is improved remarkably.

5. 发明专利

JP2009048671A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2009048671A
公开(公告)日：2009-03-05
申请号：JP2007210885
申请日：2007-08-13
申请人： Toshiba Corp , 株式会社東芝
发明人： OTSUKA NOBUAKI
IPC分类号： G11C11/413 , G11C11/412
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which improves both write characteristics and tolerance against disturb caused by variations of threshold voltage or the like and reduction of voltage, and suppresses increase in area, increase in power and deterioration of speed property. SOLUTION: The semiconductor storage device is provided with: a memory cell containing a first inverter IV1 to which an input end and output end are connected to cross respectively and a second inverter IV2; a reference supply wiring VSSCL which supplies reference voltage VSSC to the first inverter IV1; a reference supply wiring VSSCR which supplies reference voltage VSSC to the second inverter IV2; bit lines BL and /BL connected to the memory cell; and transfer gates TL1 and TL2 and transfer gates TR1 and TR2 which control impedance in the reference supply wirings VSSCL and VSSCR according to voltages of bit lines BL and /BL respectively. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体存储装置，其提高写入特性和由阈值电压等的变化引起的干扰和电压的降低，并且抑制面积的增加，功率的增加和速度的劣化属性。解决方案：半导体存储装置设置有：存储单元，其包含第一反相器IV1，输入端和输出端分别连接到第一反相器IV1和第二反相器IV2; 将参考电压VSSC提供给第一反相器IV1的参考电源线VSSCL; 向第二反相器IV2供给基准电压VSSC的基准电源配线VSSCR; 连接到存储单元的位线BL和/ BL; 以及分别根据位线BL和/ BL的电压来控制参考电源配线VSSCL和VSSCR中的阻抗的传输门TL1和TL2以及传输门TR1和TR2。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008146734A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2008146734A
公开(公告)日：2008-06-26
申请号：JP2006331992
申请日：2006-12-08
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKANO TAKESHI , YABE TOMOAKI , OTSUKA NOBUAKI
IPC分类号： G11C11/41
CPC分类号： G11C7/18
摘要： PROBLEM TO BE SOLVED: To increase the operation speed of a semiconductor memory.
SOLUTION: This semiconductor memory has sub-arrays connecting the memory cells arranged in matrixes, local bit lines connected to memory cells arranged in the column direction in the sub-arrays, global bit lines connected to the local bit lines, and a column decoder connected to the global bit lines. However, in the farthest sub-array formed in an area most apart from the column decoder among those sub-arrays, the global bit lines are not formed.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提高半导体存储器的操作速度。解决方案：该半导体存储器具有连接以矩阵排列的存储单元的子阵列，连接到子阵列中的列方向上布置的存储单元的本地位线，连接到局部位线的全局位线，以及列解码器连接到全局位线。然而，在这些子阵列中与列解码器最远的区域中形成的最远的子阵列中，不形成全局位线。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2001094048A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001094048A
公开(公告)日：2001-04-06
申请号：JP26952099
申请日：1999-09-22
申请人： TOSHIBA CORP
发明人： OTSUKA NOBUAKI , KAMEDA YASUSHI
IPC分类号： H01L27/04 , G11C7/10 , G11C11/40 , H01L21/822 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having an output impedance control circuit for performing highly accurate impedance adjustment for an output buffer circuit, even if power supply voltage is reduced in a semiconductor device having programmable impedance control function. SOLUTION: The gate terminal level of a first load transistor connected to an external resistor, whose impedance is specified is controlled, so that the voltage of the connection node becomes 1/2 the drive power supply voltage of an output buffer circuit. A second load transistor, that is the same conductor as the first load transistor and whose gate, is commonly connected to the first load transistor, and a dummy output buffer circuit that is used for impedance matching are connected in series, and the size of the dummy buffer circuit is controlled so that the drain voltage of a group of transistors of the dummy buffer circuit becomes 1/2 the drive power supply voltage of the output buffer circuit.

8. 发明专利

JP2001093297A TEST DEVICE FOR SEMICONDUCTOR 失效
公开(公告)号：JP2001093297A
公开(公告)日：2001-04-06
申请号：JP26992199
申请日：1999-09-24
申请人： TOSHIBA CORP
发明人： OTSUKA NOBUAKI
IPC分类号： G11C11/413 , G06F12/16 , G11C29/00 , G11C29/06
摘要： PROBLEM TO BE SOLVED: To suppress a peak current generated by batch selection of word lines, non-selection control, setting of a write-in level of a bit line, and batch control of recovery, when accelerated stress is applied to a memory cell in burn-in and the like and screening is performed. SOLUTION: This device is provided with a cell 11 connected to word lines WL and a pair of bit line BL, /BL, a transistor 13 conducted in a normal operation state and charging a pair of bit line, a test mode setting means setting a test mode, a control means controlling so that the transistor 13 becomes in a non-conduction state at the time of a test mode, a dummy word line DWL brought into a selection state at the time of a test mode, and a dummy cell 16 connected to a dummy word line and a pair of bit line and having same constitution as the cell 11.

9. 发明专利

JP2000163994A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JP2000163994A
公开(公告)日：2000-06-16
申请号：JP33306298
申请日：1998-11-24
申请人： TOSHIBA CORP
发明人： OTSUKA NOBUAKI
IPC分类号： G11C11/413 , G01R31/28 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/50 , G11C29/56
摘要： PROBLEM TO BE SOLVED: To shorten the test time of the setup time and hold time of input data and to improve the reliability of a test. SOLUTION: Address data are inputted to an address register 13 through a pad 11 and an input buffer 12 and used to read and write a memory core 22. When a setup and a hold time are tested, a control circuit 5 switches a multiplexer 31 to a pass side, the output side of the address register 13 and the output register 32 are connected, and the address data held in the address register 13 are transferred directly to an output register 32. Consequently, the address data of the output register 32 are read out to an external tester, etc., through an input/output pad, and it can be checked whether or not the input address data themselves are correct. Since the input address is checked directly, test can be conducted in a short time with high reliability.

10. 发明专利

JP2000101414A SEMICONDUCTOR INPUT CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JP2000101414A
公开(公告)日：2000-04-07
申请号：JP27218698
申请日：1998-09-25
申请人： TOSHIBA CORP
发明人： OTSUKA NOBUAKI , HIRABAYASHI OSAMU
IPC分类号： H01L21/8238 , G01R31/28 , G11C11/401 , G11C11/409 , G11C29/00 , G11C29/12 , H01L27/092 , H03K19/00 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor input circuit where a through-current is eliminated, while properly reflecting a logic level of an external input signal onto the inside of the circuit in a test mode. SOLUTION: This semiconductor input circuit is provided with a differential amplifier circuit which has a current mirror circuit consisting of 1st conduction type 1st and 2nd MOS transistors(TRs) 11, 12, whose gates respectively receive an external input signal and a reference level signal and whose sources are connected in common and of 2nduction type two MOS TRs 21, 22 whose drains are connected respectively to drains of the 1st and 2nd MOS TRs 11, 12. In this case, a transfer gate 30 that is on/off-controlled by a test use control signal is connected between the gate node of the current mirror circuit and an external input node, to which the external input signal is applied.

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