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1. 发明专利

JPS63293800A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS63293800A
公开(公告)日：1988-11-30
申请号：JP13080587
申请日：1987-05-27
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： IMAMIYA KENICHI , TANAKA SUMIO , MIYAMOTO JUNICHI , ATSUMI SHIGERU , OTSUKA NOBUAKI , IYAMA YUMIKO
IPC分类号： G11C29/00 , G11C16/02 , G11C16/06 , G11C16/34 , G11C17/00 , G11C29/12
摘要： PURPOSE:To secure a sufficient power supply margin by means of all access operation including normal reading operation by providing the titled memory with a circuit for changing a data reading reference in a reading mode and a program verify mode. CONSTITUTION:At the time of the program verify mode, a dummy cell 11 capable of applying earth potential to its gate is turned off and a reference potential generated at that time is expressed by V2. At the time normal reading, potential Vcc is applied to the gate of the dummy cell 11, the dummy cell 11 is turned on and generates a reference voltage shown by V1, then V1

2. 发明专利

JPH09231792A TESTING METHOD FOR SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY USED IN THE METHOD, AND TESTING APPARATUS FOR SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH09231792A
公开(公告)日：1997-09-05
申请号：JP4291696
申请日：1996-02-29
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： IYAMA YUMIKO , BANBA HIRONORI
IPC分类号： G01R31/28 , G11C29/00 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To test more ICs in a short time. SOLUTION: Input/output terminals I/O1 of ICs to be measured 10-1, 10-2, 10-n are connected to a common data line 15a. A control circuit 43 transmits address signals, data, etc., to the ICs to be measured, thereby writing and erasing data repeatedly. At a time point after data are erased, data of a status register of each IC to be measured are read out. If data of the status registers of all the ICs to be measured are OK, all the input/output terminals I/O1 are turned to a high impedance, and the data line 15a is changed to 'L'. On the other hand, if data of the status register of at least one IC to be measured are NG, the data line is turned to 'H'. Therefore, the ICs can be tested in a short time by reading a potential of the data line.

3. 发明专利

JPH02187996A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH02187996A
公开(公告)日：1990-07-24
申请号：JP743489
申请日：1989-01-13
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： IYAMA YUMIKO , MIYAMOTO JUNICHI , OTSUKA NOBUAKI , TANAKA SUMIO
IPC分类号： G11C17/00 , G11C16/06 , G11C16/28
摘要： PURPOSE:To contrive the improvement of reliability by comparing the read-out potential from a memory cell with the reference potential by a sense amplifier and executing a sense of data. CONSTITUTION:A CMOS gate circuit 49 consisting of P channel MOS transistors TR 47, 48 is provided, a gate of the TR 47 and a gate of the TR 48 are connected to a node 44 and an output node of an inverter 42, respectively, an enhancement P channel MOS TR 50 is inserted between the node 44 and a power supply voltage SW, and its gate to an output node of the gate circuit 49. When a write control signal WE is '0', and an output of the inverter 42 is '0', the power supply voltage SW is outputted from the circuit 49. Subsequently, the P channel TR 50 is turned off and a current of a path extending from the voltage SW to a ground voltage Vss comes not to flow, and it becomes '1' when the signal WE is '1' and the TR 48 in the circuit 49 is turned on, and the voltage Vss is outputted from the circuit 49. In such a way, characteristics of a dummy cell and a memory cell can be allowed to correspond with each other and high reliability is obtained.

4. 发明专利

JPH1145978A SEMICONDUCTOR MEMORY DEVICE AND VOLTAGE GENERATION CIRCUIT 失效
公开(公告)号：JPH1145978A
公开(公告)日：1999-02-16
申请号：JP20154297
申请日：1997-07-28
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： IYAMA YUMIKO , BANBA HIRONORI , ATSUMI SHIGERU
IPC分类号： G11C16/06 , G11C5/14 , G11C16/12 , G11C16/14 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To provide a voltage generation circuit in a semiconductor memory device, which can output a high potential even when the lower voltage power source is used. SOLUTION: A negative voltage generation circuit 8a is provided in booster circuit 8 which supplies a voltage to a low decoder 3 for control of a gate voltage of each cell in a memory cell array 1. When a D battery providing a low voltage is used as the power source, the negative voltage generation circuit 8a generates a high negative voltage as in an erasing mode. A voltage having an amplitude larger than that of an external power source voltage VCC, for example, a pulse signal having a VCCH amplitude obtained by boosting the voltage VCC is applied to gates of p-channel MOS transfer transistors T1, T2 and T3, so that, even when the external power is made low, the circuit can output a high voltage efficiently.

5. 发明专利

JPH06275099A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH06275099A
公开(公告)日：1994-09-30
申请号：JP5978193
申请日：1993-03-19
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： TANAKA SUMIO , IYAMA YUMIKO
IPC分类号： G11C17/00 , G11C16/06 , G11C29/00 , G11C29/56
摘要： PURPOSE:To measure a time required to read data in the case it takes always the longest time to read data. CONSTITUTION:This device is provided with a column decoder selecting circuit 1, a ROM 2 for the device, a test circuit 3, a row decoder 4 and a sense amplifier 5. The test circuit 3 has n channel type MOSFETs n0-ni respectively connected to each bit lines BL0-BLi and bit line reset transistors a0'-ai', bo'-bi'. A control signal TM is supplied to each gate electrodes of the n channel type MOSFET no-ni. When the control signal TM is a high level, a reading output circuit is switched to a test mode, a bit line in a non-selection state is set to a ground level, and a time required to read the worst data is measured. Further, when the control signal TM is a low level, the reading output circuit is switched to an ordinary data reading mode.

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