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    • 1. 发明专利
    • SEMICONDUCTOR DEVICE AND ITS MANUFACTURE
    • JPH09321224A
    • 1997-12-12
    • JP13629796
    • 1996-05-30
    • TOSHIBA CORP
    • ABE SEIGOOKAMOTO RINTAROU
    • H01L27/04H01L21/265H01L21/822
    • PROBLEM TO BE SOLVED: To provide resistance elements which highly precisely control a sheet resistance by permitting the first resistance element to contain first conductive impurities and a second resistance element to contain first and second conductive impurities and showing a resistance value generated by a density difference between the first and second conductive impurities. SOLUTION: A low resistance element formation scheduled area and a high resistance element formation scheduled area in a polycrystalline Si layer are doped with boron at the density of not less than 1×10 /cm , 8×10 /cm , for example, with ion implanting so as to form the low resistance element in the low resistance element formation scheduled area. Then, the part of the low resistance element is doped with phosphorous only in the high resistance element formation scheduled area, at the density of not less than 1×10 /cm , 7×10 /cm , for example, with ion implanting so as to form the high resistance element in the high resistance element formation scheduled areas. Consequently, the high resistance element which is equal to a case when 34 P-type boron and 22 N-type phosphorous are compensate and 12 boron exist and which has less variance of the resistance value can be provided.
    • 3. 发明专利
    • Solid-state image pick up device
    • 固态图像拾取器件
    • JPH11274457A
    • 1999-10-08
    • JP7089298
    • 1998-03-19
    • Toshiba Corp株式会社東芝
    • YAMASHITA HIROSHIIHARA HISANORIINOUE IKUKOYAMAGUCHI TETSUYANAKAMURA NOBUONARUSE HIROSHIIGUMA HIDEMIKISHIBATA HIDENORIMAKABE AKIRAABE SEIGONOMACHI EIKOSHIOYAMA YOSHIYUKIHORI MIKIKONOZAKI HIDETOSHI
    • H01L27/146H04N5/335H04N5/355H04N5/361H04N5/374
    • H01L27/14609
    • PROBLEM TO BE SOLVED: To facilitate ejection of a signal charge at a signal accumulating part and to prevent deterioration of dynamic range in an element, thermal noise, residual image, etc., in the dark from generating, even when the pixel size of a MOS type solid-state image pick up device is reduced, a read gate voltage is deteriorated and a well concentration is increased.
      SOLUTION: On the surface of a p-type silicon substrate 21, a (p)
      + type diffusion layer 23 which constitutes a photoelectric conversion region 22 and the drain 24 of a read MOS type field effect transistor are formed. At the lower part of the (p)
      + diffusion layer 23, a signal accumulating part 25 formed of an (n) type diffusion layer is formed adjacent to the (p)
      + type diffusion layer. On the surface of the silicon substrate 21, the gate electrode 26 of a MOS type field effect transistor is provided between the (p)
      + diffusion layer 23 and the drain 24. The edge part of the gate electrode 26 of the MOS transistor of the signal accumulating part 25 is protruded, having its edge position extended downward from the read gate electrode 26 of the diffusion layer 23 further than the edge part of the read gate electrode 26 of the (p)
      + diffusion layer 23 provided on the surface of the silicon substrate 21.
      COPYRIGHT: (C)1999,JPO
    • 要解决的问题:为了便于在信号累积部分处的信号电荷的排出,并且防止在黑暗中的元件,热噪声,残留图像等中的动态范围的劣化产生,即使当像素尺寸 MOS型固体摄像装置减少,读栅极电压劣化,阱浓度增加。 解决方案:在p型硅衬底21的表面上,形成构成光电转换区22的(p)+型扩散层23和读取MOS型场效应晶体管的漏极24。 在(p)+扩散层23的下部,形成与(p)+型扩散层相邻的(n)型扩散层形成的信号存储部25。 在硅衬底21的表面上,MOS型场效应晶体管的栅极26设置在(p)+扩散层23和漏极24之间.MOS晶体管的栅电极26的边缘部分 信号累积部25的边缘位置比扩散层23的读取栅电极26向下延伸的边缘位置比设置在(p)+扩散层23的读取栅电极26的边缘部分突出 硅衬底21的表面。
    • 5. 发明专利
    • SOLID-STATE IMAGE SENSING DEVICE
    • JPH07153930A
    • 1995-06-16
    • JP29843193
    • 1993-11-29
    • TOSHIBA CORP
    • ABE SEIGO
    • H01L27/148
    • PURPOSE:To prevent unnecessary gate electrode material from remaining on the sides of a first gate electrode by forming a groove in a charge transfer path, burying the first gate electrode in this groove interposing a first gate insulating film, and forming a second gate electrode so as to lap over the first gate electrode interposing a second insulating film. CONSTITUTION:A groove 130 is formed in a shape corresponding to a first gate electrode 132 by etching a part of a region for a charge transfer path 122 to be formed. Next a charge transfer path 122 is formed by selective ion implantation. Following this, polysilicon is deposited on the whole surface, and phosphorus is diffused after that. And etchback is performed, and polysilicon deposited on other than the groove 130 is removed and a first gate electrode 132 is formed. The whole surface is thermally oxidized, and a silicon oxide film 133 is formed. After that, polysilicon is deposited on the whole surface of a substrate, and then phosphorus is diffused. And a second gate electrode 134 is formed by pattern etching. It becomes possible to prevent unnecessary electrode material from remaining on the sides of the first gate electrode, when the second electrode is formed.
    • 6. 发明专利
    • MANUFACTURE OF SEMICONDUCTOR DEVICE
    • JPH11186377A
    • 1999-07-09
    • JP35125397
    • 1997-12-19
    • TOSHIBA CORP
    • ABE SEIGO
    • H01L27/146H01L21/76
    • PROBLEM TO BE SOLVED: To improve the process margin, with respect to remaining of field element isolating insulation film on the sidewall or thinning of a gate insulation film of an MOS type image-pickup element having a field element isolation structure. SOLUTION: This manufacturing method comprises the steps of depositing a polycrystalline Si film 13 with a concn. gradient increasing the concn. at its lower portion, e.g. on a semiconductor substrate 11 via a gate insulation film 12, depositing an Si nitride film 14, self-alignedly forming a channel stop layer 17 via openings 16, stripping a resist film 15, forming a side oxide film 28 on the sidewall of the Si film 13, embedding a CVD oxide film 19 in the openings 16, and finally removing the Si nitride film 14 and Si film 13 to form a CVD field element isolating insulation film 20 composed of the embedded CVD oxide film 19 and sidewall oxide film 18.
    • 7. 发明专利
    • FABRICATION OF SEMICONDUCTOR DEVICE
    • JPH07273121A
    • 1995-10-20
    • JP6185494
    • 1994-03-31
    • TOSHIBA CORP
    • ABE SEIGOKIMURA KOJI
    • H01L21/76H01L21/322
    • PURPOSE:To enhance the reliability of a semiconductor device by implanting ions exhibiting the gettering effect into the side wall face of an isolation trench and effecting the gettering through heat treatment thereby decreasing the impurities, which cause to deteriorate the characteristics of semiconductor, effectively in a semiconductor substrate. CONSTITUTION:An isolation trench 31 is made at a specified depth in a semiconductor substrate 11 and impurity ions 41 exhibiting the gettering effect are implanted into the side wall face of the trench 31. It is then heat treated to effect the gettering and the region 51 implanted with the impurity ions 41 is removed. Carbon, phosphorus or boron ions are rotary implanted at a predetermined angle with respect to the side wall face of the trench 31. The heat treatment after ion implantation is effected in two stages, i.e., a first heat treatment by RTA and a second heat treatment by FA.