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1. 发明专利

JP2006313771A Epitaxial substrate for group iii nitride semiconductor element 审中-公开
标题翻译：用于III族氮化物半导体元件的外延衬底
公开(公告)号：JP2006313771A
公开(公告)日：2006-11-16
申请号：JP2005134926
申请日：2005-05-06
申请人： Showa Denko Kk , 昭和電工株式会社
发明人： BANDO AKIRA
IPC分类号： H01L21/205 , H01L21/20 , H01L29/207 , H01L33/06 , H01L33/32 , H01S5/323
摘要： PROBLEM TO BE SOLVED: To provide an epitaxial substrate for a group III nitride semiconductor element which is suitable to manufacturing of a group III nitride semiconductor light-emitting element having excellent light-emitting efficiency, reverse breakdown voltage characteristic, and electrostatic breakdown voltage characteristic. SOLUTION: The epitaxial substrate for a group III nitride semiconductor element consists of a substrate having a surface roughness (Ra) of not more than 1 nm, and a group III nitride semiconductor layer directly laminated on the substrate. In the epitaxial substrate, the group III nitride semiconductor layer consists of a plurality of layers contacting with each other, and at least one of the plurality of layers is a layer having a transition density of not more than 1×10 7 cm -2 . COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供适合于制造具有优异的发光效率，反向击穿电压特性和静电击穿的III族氮化物半导体发光元件的III族氮化物半导体元件的外延衬底电压特性。解决方案：用于III族氮化物半导体元件的外延衬底由表面粗糙度（Ra）不大于1nm的衬底和直接层叠在衬底上的III族氮化物半导体层组成。在外延基板中，III族氮化物半导体层由多个彼此接触的层组成，并且多个层中的至少一个层是具有不大于1×10 < / SP>厘米 -2 。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2009184899A Group iii nitride semiconductor epitaxial substrate and its manufacturing method 有权
标题翻译：第III组氮化物半导体外延衬底及其制造方法
公开(公告)号：JP2009184899A
公开(公告)日：2009-08-20
申请号：JP2008029456
申请日：2008-02-08
申请人： Showa Denko Kk , 昭和電工株式会社
发明人： BANDO AKIRA , AMANO HIROSHI
IPC分类号： C30B29/38 , C23C16/04 , C23C16/34 , C30B25/04 , H01L21/205 , H01L31/10 , H01L33/16 , H01L33/32 , H01S5/02
CPC分类号： C30B29/403 , C30B25/02 , H01L21/0237 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02642 , H01L21/02647 , H01L31/03048 , H01L31/1844 , H01L33/0075 , H01S5/32341 , H01S2304/12 , Y02E10/544 , Y02P70/521
摘要： PROBLEM TO BE SOLVED: To provide a group III nitride semiconductor epitaxial substrate in which the penetration dislocation to a perpendicular direction is inhibited and the crystal quality is excellent. SOLUTION: The group III nitride semiconductor epitaxial substrate 10 comprises forming an ELO growth layer 4 of the composition of Al x Ga 1-x N (0≤x≤1) on a group III nitride layer 2 formed on a substrates 1, wherein the ELO (Epitaxial Lateral Overgrowth) growth layer 4 is formed using a mask pattern 3 consisting of carbon formed on the group III nitride layer 2. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供抑制垂直方向的穿透位错并且晶体质量优异的III族氮化物半导体外延基板。解决方案：III族氮化物半导体外延衬底10包括：形成由下列组成组成的ELO生长层4：（1≤x≤0.3） 1）在形成在基板1上的III族氮化物层2上，其中使用由形成在III族氮化物层2上的碳组成的掩模图案3形成ELO（外延横向生长）生长层4.版权所有：（C）2009，JPO＆INPIT

3. 发明专利

JP2006273618A AlGaN SUBSTRATE AND ITS MANUFACTURING METHOD 有权
标题翻译： AlGaN衬底及其制造方法
公开(公告)号：JP2006273618A
公开(公告)日：2006-10-12
申请号：JP2005092079
申请日：2005-03-28
申请人： Showa Denko Kk , 昭和電工株式会社
发明人： AMANO HIROSHI , BANDO AKIRA
IPC分类号： C30B29/38 , C23C16/34
CPC分类号： C03B25/02 , C30B25/02 , C30B29/403 , H01L21/0237 , H01L21/0242 , H01L21/0254 , H01L21/0262 , H01L33/0075 , Y10S117/915
摘要： PROBLEM TO BE SOLVED: To provide an Al x Ga 1-x N (0≤x≤1) substrate which is used for manufacturing a group III nitride semiconductor device. SOLUTION: An Al x Ga 1-x N (0≤x≤1) layer is formed on a base material using one of sapphire, SiC, Si, ZnO and Ga 2 O 3 as the base material by an MOCVD method and then the Al x Ga 1-x N (0≤x≤1) substrate is manufactured by removing the base material under the conditions that growing velocity is 5 μm/hour or higher, the V/III ratio in a raw material is 1,000 or less and the temperature of film formation is 1,200°C or higher. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供用于制造III族氮化物半导体的Al x Ga 1-x N（0≤x≤1）设备。解决方案：使用蓝宝石，SiC，Si等中的一种，在基材上形成Al（SB）x Ga 1-x N（0≤x≤1）通过MOCVD法将ZnO和Ga O 3 作为基材，然后再将Al x SB > N（0≤x≤1）基板是通过在生长速度为5μm/小时以上，原料的V / III比为1000以下的条件下除去基材而成膜，成膜温度为1200℃以上。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2005340789A Group iii nitride semiconductor light-emitting element 审中-公开
标题翻译：第III组氮化物半导体发光元件
公开(公告)号：JP2005340789A
公开(公告)日：2005-12-08
申请号：JP2005126162
申请日：2005-04-25
申请人： Showa Denko Kk , 昭和電工株式会社
发明人： MIKI HISAYUKI , BANDO AKIRA , UDAGAWA TAKASHI
IPC分类号： H01L33/06 , H01L33/32 , H01L33/42 , H01L33/62 , H01L33/00
摘要： PROBLEM TO BE SOLVED: To provide a group III nitride light-emitting element that has improved flatness of an emission layer and improved crystallinity and does not cause a decrease in emission output even after a long-term energization. SOLUTION: In the group III nitride semiconductor light-emitting element that is formed on a crystal substrate and has n-type and p-type group III nitride semiconductors expressed by the following composition formula, an emission layer includes a region doped with germanium (element symbol:Ge). In the emission layer, preferably Ge concentration is changed periodically or an undoped region and a region doped with Ge are alternately laminated periodically. The above composition formula is expressed by Al X Ga Y In Z N 1-a M a (however, 0≤X≤1, 0≤Y≤1, 0≤Z≤1, and X+Y+Z=1), and the symbol M indicates a group V element separate from nitrogen (N) and 0≤a COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种III族氮化物发光元件，其具有改善的发光层的平坦度和改善的结晶度，并且即使在长期通电之后也不会导致发射输出的降低。解决方案：在由晶体基板上形成并具有由以下组成式表示的n型和p型III族氮化物半导体的III族氮化物半导体发光元件中，发光层包括掺杂有锗（元素符号：Ge）。在发光层中，优选地，周期性地改变Ge浓度或不掺杂区域和掺杂有Ge的区域。上述组成式由下式表示：＆lt; SB＆gt;＆lt; SB＆gt; Y＆lt; SB＆lt; SB＆gt; （但是，0≤X≤1,0≤Y≤1,0≤Z≤1，X + Y + Z = 1），符号M表示与氮（N）分开的V族元素， 0≤a<1。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2011054639A Apparatus and method for manufacturing compound semiconductor, and compound semiconductor 有权
标题翻译：用于制造化合物半导体和化合物半导体的装置和方法
公开(公告)号：JP2011054639A
公开(公告)日：2011-03-17
申请号：JP2009200204
申请日：2009-08-31
申请人： Showa Denko Kk , 昭和電工株式会社
发明人： YASUHARA HIDEKI , BANDO AKIRA
IPC分类号： H01L21/205 , C23C16/458 , H01L21/683
CPC分类号： C23C16/4583 , C23C16/303 , C23C16/4584 , C23C16/4585 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/68735 , H01L21/68764 , H01L21/68771
摘要： PROBLEM TO BE SOLVED: To equalize temperature on a surface of a substrate, on which a crystal of a compound semiconductor is epitaxially grown, in manufacture of the compound semiconductor by using an MOCVD method. SOLUTION: A compound semiconductor manufacturing device forms a compound semiconductor layer by using a metal organic chemical vapor deposition method. The device includes a reaction container, a holder which is arranged in the reaction container and on which an object to be formed is placed so that a face to be formed of the object to be formed directed upward, and a raw material supply port supplying material gas of the compound semiconductor into the reaction container from outside. The holder has a support member for supporting the body to be formed such that an upper surface of the holder on which the object to be formed is placed and a lower surface of the object to be formed hold a prescribed interval. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了使通过MOCVD法在化合物半导体的制造中外延生长化合物半导体的晶体的表面上的温度平衡。解决方案：化合物半导体制造装置通过使用金属有机化学气相沉积法形成化合物半导体层。该装置包括反应容器，保持器，其布置在反应容器中，并且待成形物体放置成使得要形成的要形成的面朝向上方，以及原料供给口供给材料化合物半导体的气体从外部进入反应容器。保持器具有用于支撑要形成的主体的支撑构件，使得待放置物体的保持器的上表面和待形成的物体的下表面保持规定的间隔。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2011049309A Method for manufacturing compound semiconductor 有权
标题翻译：制造化合物半导体的方法
公开(公告)号：JP2011049309A
公开(公告)日：2011-03-10
申请号：JP2009195727
申请日：2009-08-26
申请人： Showa Denko Kk , 昭和電工株式会社
发明人： YASUHARA HIDEKI , BANDO AKIRA
IPC分类号： H01L21/205 , C23C16/52
摘要： PROBLEM TO BE SOLVED: To accurately measure a surface temperature of a layer of a compound semiconductor laminated on a substrate, in manufacturing the compound semiconductor using an organometallic vapor deposition. SOLUTION: A substrate holding body (holding body) 30 mounted with a compound semiconductor substrate (body to be formed: sapphire substrate) 40 is installed on an inside of a reaction container, in this method for manufacturing the compound semiconductor using the organometallic vapor deposition, the compound semiconductor is epitaxy-grown (compound semiconductor layer 100) on a surface of the compound semiconductor substrate 40, by heating the substrate holding body (holding body) 30 installed on the inside of the reaction container, to react with a raw gas of the compound semiconductor supplied into the reaction container, and the surface temperature of the compound semiconductor layer 100 is measured using an infrared ray within 8-14 μm of wavelength range by a radiation thermometer 90a. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了精确地测量层叠在基板上的化合物半导体层的表面温度，在使用有机金属气相沉积制造化合物半导体时。解决方案：在该反应容器的内侧安装有安装有化合物半导体基板（待形成物体）蓝宝石基板40的基板保持体（保持体）30，在该化合物半导体的制造方法中，使用通过加热安装在反应容器内部的基板保持体（保持体）30，化合物半导体在化合物半导体基板40的表面上外延生长（化合物半导体层100），与供给反应容器的化合物半导体的原料气体和化合物半导体层100的表面温度通过辐射温度计90a使用波长范围在8〜14μm的红外线进行测定。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2006049848A n-TYPE GROUP III NITRIDE SEMICONDUCTOR LAMINATED STRUCTURE 审中-公开
标题翻译： n型III类氮化物半导体层叠结构
公开(公告)号：JP2006049848A
公开(公告)日：2006-02-16
申请号：JP2005186599
申请日：2005-06-27
申请人： Showa Denko Kk , 昭和電工株式会社
发明人： BANDO AKIRA
IPC分类号： H01L21/205 , H01L33/06 , H01L33/12 , H01L33/14 , H01L33/32 , H01L33/50
摘要： PROBLEM TO BE SOLVED: To provide a low-resistance n-type Group III nitride semiconductor layer having excellent flatness and few cracks and pits, and also to provide a Group III nitride semiconductor light emitting element having excellent light emitting efficiency with low forward voltage using the n-type Group III nitride semiconductor layer. SOLUTION: An n-type Group III nitride semiconductor laminated structure is formed by laminating an n-type impurity atom higher concentration layer and an n-type impurity atom lower concentration layer alternately. Further, the Group III nitride semiconductor light emitting element is constituted by providing the n-type Group III nitride semiconductor laminated structure between a substrate and a light emitting layer of Group III nitride semiconductor. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供具有优异的平坦度和很少的裂纹和凹坑的低电阻n型III族氮化物半导体层，并且还提供具有优异的发光效率的III族氮化物半导体发光元件使用n型III族氮化物半导体层的正向电压。解决方案：n型III族氮化物半导体层叠结构通过交替层叠n型杂质原子较高浓度层和n型杂质原子低浓度层而形成。此外，通过在衬底和III族氮化物半导体的发光层之间提供n型III族氮化物半导体层叠结构，构成III族氮化物半导体发光元件。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2006013472A Iii group nitride semiconductor light emitting device 审中-公开
标题翻译： III组氮化物半导体发光器件
公开(公告)号：JP2006013472A
公开(公告)日：2006-01-12
申请号：JP2005150999
申请日：2005-05-24
申请人： Showa Denko Kk , 昭和電工株式会社
发明人： KOBAYAKAWA MASATO , OKUYAMA MINEO , BANDO AKIRA , TOMOSAWA HIDEKI , MIKI HISAYUKI
IPC分类号： H01L33/06 , H01L33/32 , H01L33/38 , H01L33/42
摘要： PROBLEM TO BE SOLVED: To provide a III group nitride semiconductor light emitting device which is excellent in luminescent characteristics, and in which a decline in luminescent output caused by aging and a change in characteristics of such as decrease in inverse withstand voltage are very rare. SOLUTION: The III group nitride semiconductor light emitting device includes a III group nitride semiconductor (its composition formula is Al x Ga y In z N 1-a M a ; 0≤x≤1, 0≤y≤1, 0≤z≤1, and x+y+z=1, and M expresses another group V element different from nitrogen (N) and is 0≤a COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供发光特性优异的III族氮化物半导体发光器件，其中由老化引起的发光输出下降和反向耐受电压降低等特性的变化是很稀少。解决方案：III族氮化物半导体发光器件包括III族氮化物半导体（其组成式为Al SB SB x Y x SB > N 1-a a ;0≤x≤1,0≤y≤1,0≤z≤1，x + y + z = 1，以及 M表示形成在晶体基板上的与氮（N）不同的另一V族元素，为0≤a<1，其中，所述III族氮化物半导体发光器件包括n型层，发光层和p- 类型层从晶体衬底侧开始，在n型层中掺杂锗（Ge）的区域和比n型层和n型层之间的n型层低的载流子浓度的前端层晶体基板。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2005340762A Group iii nitride semiconductor light-emitting element 审中-公开
标题翻译：第III组氮化物半导体发光元件
公开(公告)号：JP2005340762A
公开(公告)日：2005-12-08
申请号：JP2005017991
申请日：2005-01-26
申请人： Showa Denko Kk , 昭和電工株式会社
发明人： MIKI HISAYUKI , BANDO AKIRA , UDAGAWA TAKASHI
IPC分类号： H01L33/06 , H01L33/32 , H01L33/42 , H01L33/62 , H01L33/00
摘要： PROBLEM TO BE SOLVED: To provide a light-emitting element having improved emission output without losing the flatness of a semiconductor layer and crystallinity in a group III nitride semiconductor light-emitting element containing Ge in a dopant. SOLUTION: In the group III nitride semiconductor light-emitting element that is formed on a crystal substrate and has n-type and p-type group III nitride semiconductors expressed by the following composition formula, an n-type electrode contract layer includes a region doped with germanium (element symbol: Ge), and the emission layer includes a non-doped region or a region doped with at least one type of element selected from among a group comprising Si, C, Sn, and Pb. In the n-type electrode contact layer, preferably Ge concentration is changed periodically or a region doped with Ge and an undoped region are alternately laminated periodically. The above composition formula is expressed by AlXGaYInZN1-aMa (however, 0≤X≤1, 0≤Y≤1, 0≤Z≤1, and X+Y+Z=1), and the symbol M indicates a group V element separate from nitrogen (N) and 0≤a COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种具有改善的发射输出的发光元件，而不会在掺杂剂中含有Ge的III族氮化物半导体发光元件中丧失半导体层的平坦度和结晶度。解决方案：在形成在晶体基板上并具有由以下组成式表示的n型和p型III族氮化物半导体的III族氮化物半导体发光元件中，n型电极接合层包括掺杂有锗（元素符号：Ge）的区域，并且发光层包括掺杂有选自包含Si，C，Sn和Pb的组中的至少一种类型的元素的非掺杂区域或区域。在n型电极接触层中，优选地，周期性地改变Ge浓度周期性地改变掺杂有Ge和未掺杂区域的区域。上述组成式由AlXGaYInZN1-aMa（但是，0≤X≤1,0≤Y≤1,0≤Z≤1，X + Y + Z = 1）表示，符号M表示V族元素与氮（N）和0≤a<1分离。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2013118213A Silicon carbide semiconductor device and manufacturing method of the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2013118213A
公开(公告)日：2013-06-13
申请号：JP2011263674
申请日：2011-12-01
申请人： Showa Denko Kk , 昭和電工株式会社
发明人： BANDO AKIRA
IPC分类号： H01L29/47 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device and a manufacturing method of the same, which can inspect presence or absence of defects from a surface of a wafer more simply and in a shorter time and with higher resolution than in the past and in a state of the wafer before singulation into chips.SOLUTION: A silicon carbide semiconductor device of an embodiment comprises: a silicon carbide substrate 1; an n-type silicon carbide layer 2 formed on the silicon carbide substrate 1; p-type impurity regions 5 formed close to a surface of the n-type silicon carbide layer 2; and a Schottky electrode 11 composed of a transparent conductive film and formed on the p-type impurity regions 5 and the n-type silicon carbide layer 2.
摘要翻译：解决的问题：为了提供一种碳化硅半导体器件及其制造方法，其可以更简单地并且在更短的时间内以更高的分辨率来检查来自晶片表面的缺陷的存在或不存在过去并处于晶片状态，然后再分割成芯片。解决方案：实施例的碳化硅半导体器件包括：碳化硅衬底1; 形成在碳化硅衬底1上的n型碳化硅层2; 在n型碳化硅层2的表面附近形成的p型杂质区域5; 和由p型杂质区域5和n型碳化硅层2形成的透明导电膜构成的肖特基电极11.（C）2013，JPO＆INPIT

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