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1. 发明专利

JP2014207286A 半導体装置、表示装置及び半導体装置の作製方法有权
标题翻译：半导体器件，显示器件和半导体器件的制造方法
公开(公告)号：JP2014207286A
公开(公告)日：2014-10-30
申请号：JP2013083132
申请日：2013-04-11
申请人：株式会社半導体エネルギー研究所 , Semiconductor Energy Lab Co Ltd , シャープ株式会社 , Sharp Corp
发明人： HIZUKA JUNICHI , OKAZAKI KENICHI , TAKAHASHI MASAHIRO , MATSUO TAKUYA , MORI SHIGEYASU , KANZAKI YOSUKE , MATSUKIZONO HIROSHI
IPC分类号： H01L29/786
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/04 , H01L29/045 , H01L29/66969 , H01L29/78618 , H01L29/78696
摘要：【課題】チャネル長の縮小を抑制した新規な半導体装置を提供する。【解決手段】結晶部を含む酸化物半導体層112と、前記酸化物半導体層112に接するソース電極層108及びドレイン電極層110と、を有し、前記酸化物半導体層112は、チャネル形成領域と、前記ソース電極層108及び前記ドレイン電極層110と接するn型領域112aと、を有し、前記チャネル形成領域と、前記n型領域112aで、前記結晶部の結晶方向が異なることを特徴とする半導体装置である。【選択図】図1
摘要翻译：要解决的问题：提供抑制沟道长度减小的新的半导体器件。解决方案：半导体器件包括：包括晶体部分的氧化物半导体层112; 与氧化物半导体层112接触的源极电极层108和漏电极层110.氧化物半导体层112具有沟道形成区域和与源电极层108和漏极接触的n型区域112a 电极层110.晶体部分中的晶体取向在沟道形成区域和n型区域112a之间不同。

2. 发明专利

JP2009004582A Semiconductor device manufacturing method, display device manufacturing method, semiconductor device, and display device 审中-公开
标题翻译：半导体器件制造方法，显示器件制造方法，半导体器件和显示器件
公开(公告)号：JP2009004582A
公开(公告)日：2009-01-08
申请号：JP2007164298
申请日：2007-06-21
申请人： Sharp Corp , シャープ株式会社
发明人： MORI SHIGEYASU , YASUMATSU TAKUTO , KIMURA TOMOHIRO
IPC分类号： H01L29/786 , H01L21/316 , H01L21/318 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method that can form each gate insulating film with excellent film quality in a plurality of thin-film transistors when the plurality of the thin-film transistors, respectively having a gate insulating film with a different film-thickness, are formed on the same substrate. SOLUTION: The semiconductor device manufacturing method is used for manufacturing a semiconductor device that includes first/second thin-film transistors provided on a substrate and respectively having a semiconductor layer and a gate insulating film with a mutually different film-thickness. The manufacturing method has a step for forming a lower gate-insulating film, having wet-etching resistance, in each formation region of the first/second thin-film transistors, a step for forming an upper gate-insulating film, having wet-etching solubility, in each formation region of the first/second thin-film transistors, and a step for removing the upper gate-insulating film by wet-etching in either of the formation regions of the first/second thin-film transistors. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件制造方法，当分别具有栅极绝缘膜的多个薄膜晶体管时，可以在多个薄膜晶体管中形成具有优异的薄膜质量的每个栅极绝缘膜在同一基板上形成不同的膜厚度。解决方案：半导体器件制造方法用于制造半导体器件，该半导体器件包括设置在衬底上并分别具有相互不同膜厚度的半导体层和栅极绝缘膜的第一/第二薄膜晶体管。该制造方法具有在第一/第二薄膜晶体管的每个形成区域中形成具有耐湿蚀刻性的下部栅极绝缘膜的步骤，用于形成上部栅极绝缘膜的步骤，具有湿蚀刻在第一/第二薄膜晶体管的每个形成区域中的溶解度以及通过在第一/第二薄膜晶体管的任一个形成区域中的湿法蚀刻去除上部栅极绝缘膜的步骤。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2008242136A Exposure device, exposure method, and manufacturing method of liquid crystal display device 审中-公开
标题翻译：曝光装置，曝光方法和液晶显示装置的制造方法
公开(公告)号：JP2008242136A
公开(公告)日：2008-10-09
申请号：JP2007083476
申请日：2007-03-28
申请人： Sharp Corp , シャープ株式会社
发明人： MORI SHIGEYASU , KONDO TSUTOMU , MADONO HIROYUKI
IPC分类号： G03F7/20 , G02F1/1368 , G09F9/00 , G09F9/35 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide an exposure device and an exposure method for forming both small-sized patterns and large-sized patterns with satisfactory resolution properties by a simple configuration, and a manufacturing method of liquid crystal display devices using the exposure device. SOLUTION: An illuminating optical system 1 radiates photomasks 20A and 20B with light. Projection optical systems 2A and 2B projects the light irradiated to the photomasks 20A and 20B, onto a photoresist 32. The exposure device 10 has a plurality of projection optical systems 2A and 2B for one illuminating optical system 1 and is so configured that the plurality of projection optical systems 2A and 2B have resolutions different from each other. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于通过简单的结构形成具有令人满意的分辨率特性的小尺寸图案和大尺寸图案的曝光装置和曝光方法，以及使用曝光的液晶显示装置的制造方法设备。解决方案：照明光学系统1用光照射光掩模20A和20B。投影光学系统2A和2B将照射到光掩模20A和20B的光投影到光致抗蚀剂32上。曝光装置10具有用于一个照明光学系统1的多个投影光学系统2A和2B，并且被配置为使得多个投影光学系统2A和2B具有彼此不同的分辨率。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2007311747A Method of manufacturing semiconductor device, semiconductor device, and display 审中-公开
标题翻译：制造半导体器件，半导体器件和显示器的方法
公开(公告)号：JP2007311747A
公开(公告)日：2007-11-29
申请号：JP2006332044
申请日：2006-12-08
申请人： Sharp Corp , シャープ株式会社
发明人： MIHOYA TAKUSHI , MORI SHIGEYASU
IPC分类号： H01L21/336 , H01L21/768 , H01L23/522 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can achieve both smaller design rules and an increased manufacturing yield, a semiconductor device, and a display. SOLUTION: A semiconductor device comprises a base coat film, a semiconductor layer, a gate insulation film, and an interlayer insulation film, which are formed in this order. An opening is formed at each of some regions of the semiconductor layer so as to penetrate the gate insulation film and the interlayer insulation film. A method of manufacturing the semiconductor device comprises: a process of anisotropically etching the interlayer insulation film to form upper portions of the openings; and a process of selectively and isotropically etching the gate insulation film and an upper portion of the interlayer insulation film to form lower portions of the openings and to taper the upper portions of the openings. The base coat film has an insulation layer that functions as an etching stopper when the gate insulation film is isotropically etched. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以实现较小设计规则和提高制造成品率的半导体器件的制造方法，半导体器件和显示器。解决方案：半导体器件包括依次形成的基底涂层膜，半导体层，栅极绝缘膜和层间绝缘膜。在半导体层的一些区域的每一个处形成开口，以穿透栅极绝缘膜和层间绝缘膜。制造半导体器件的方法包括：各向异性蚀刻层间绝缘膜以形成开口的上部的工艺; 以及选择性地和各向同性地蚀刻栅极绝缘膜和层间绝缘膜的上部以形成开口的下部并使开口的上部变细的方法。底涂层膜具有绝缘层，当绝缘膜被各向同性地蚀刻时，该绝缘层用作蚀刻阻挡层。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2014207285A 表示装置及び電子機器有权
标题翻译：显示设备和电子设备
公开(公告)号：JP2014207285A
公开(公告)日：2014-10-30
申请号：JP2013083131
申请日：2013-04-11
申请人：株式会社半導体エネルギー研究所 , Semiconductor Energy Lab Co Ltd , シャープ株式会社 , Sharp Corp
发明人： HIZUKA JUNICHI , KATAYAMA MASAHIRO , SHIMA YUKINORI , OKAZAKI KENICHI , MATSUO TAKUYA , MORI SHIGEYASU , KANZAKI YOSUKE , MATSUKIZONO HIROSHI
IPC分类号： H01L29/786 , G02F1/1368 , H01L21/336
CPC分类号： H01L27/1225 , H01L23/3121 , H01L23/564 , H01L27/1248 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要：【課題】トランジスタの電気特性の変動を抑制すると共に、信頼性を向上させる。【解決手段】画素部104と、前記画素部の外側に設けられる駆動回路部106と、を有し、前記画素部は、画素トランジスタと、前記画素トランジスタを覆う無機材料で形成される第1の絶縁層122と、前記第1の絶縁層上に設けられ、且つ有機材料で形成される第2の絶縁層124と、前記第2の絶縁層上に設けられ、且つ無機材料で形成される第3の絶縁層128と、を有し、前記駆動回路部は、前記画素トランジスタに信号を供給する駆動トランジスタと、前記駆動トランジスタを覆う前記第1の絶縁層と、を有し、前記駆動回路部において、前記第2の絶縁層は形成されていない表示装置である。【選択図】図1
摘要翻译：要解决的问题：抑制晶体管的电特性的变化并提高晶体管的可靠性。解决方案：显示装置具有设置在像素部分外部的像素部分104和驱动电路部分106。像素部分包括像素晶体管，覆盖像素晶体管并由无机材料形成的第一绝缘层122，设置在第一绝缘层上并由有机材料形成的第二绝缘层124和第三绝缘层绝缘层128，其设置在第二绝缘层上并由无机材料形成。驱动电路部分包括用于向像素晶体管提供信号的驱动晶体管和覆盖驱动晶体管的第一绝缘层。在驱动电路部分中，不形成第二绝缘层。

6. 发明专利

JP2014090068A Display device and electronic apparatus 有权
标题翻译：显示设备和电子设备
公开(公告)号：JP2014090068A
公开(公告)日：2014-05-15
申请号：JP2012238918
申请日：2012-10-30
申请人： Semiconductor Energy Lab Co Ltd , 株式会社半導体エネルギー研究所 , Sharp Corp , シャープ株式会社
发明人： HIZUKA JUNICHI , SHIMA YUKINORI , HOSAKA HIROYASU , OKAZAKI KENICHI , MATSUO TAKUYA , MORI SHIGEYASU , KANZAKI YOSUKE , MATSUKIZONO HIROSHI
IPC分类号： H01L21/318 , G02F1/1368 , G09F9/30 , H01L21/312 , H01L21/316 , H01L21/336 , H01L29/786
CPC分类号： H01L27/1225 , H01L27/3262
摘要： PROBLEM TO BE SOLVED: To suppress variation in electrical characteristics of a transistor, and to improve reliability thereof.SOLUTION: A display device has a pixel part 104 and a driving circuit part 106 provided outside the pixel part. The pixel part has a pixel transistor 252, a first insulating film 124 covering the pixel transistor and formed of an inorganic material, a second insulating film 126 provided on the first insulating film and formed of an organic material, and a third insulating film 130 provided on the second insulating film and formed of an inorganic material. The driving circuit part has a driving transistor 250 for supplying a signal to the pixel transistor, the first insulating film covering the driving transistor, and the second insulating film formed on the first insulating film. The display device has, in the driving circuit part, either a region in which the third insulating film is not formed on the second insulating film or a region in which the second insulating film is not covered with the third insulating film.
摘要翻译：要解决的问题：抑制晶体管的电特性的变化并提高其可靠性。解决方案：显示装置具有设置在像素部分外部的像素部分104和驱动电路部分106。像素部分具有像素晶体管252，覆盖像素晶体管并由无机材料形成的第一绝缘膜124，设置在第一绝缘膜上并由有机材料形成的第二绝缘膜126和设置在第一绝缘膜130上的第三绝缘膜130 在第二绝缘膜上并由无机材料形成。驱动电路部分具有用于向像素晶体管提供信号的驱动晶体管250，覆盖驱动晶体管的第一绝缘膜和形成在第一绝缘膜上的第二绝缘膜。显示装置在驱动电路部分中，在第二绝缘膜上没有形成第三绝缘膜的区域或第二绝缘膜未被第三绝缘膜覆盖的区域。

7. 发明专利

JP2011003650A Multilayer wiring board, and semiconductor device having the same 审中-公开
标题翻译：多层接线板及具有相同功能的半导体器件
公开(公告)号：JP2011003650A
公开(公告)日：2011-01-06
申请号：JP2009144284
申请日：2009-06-17
申请人： Sharp Corp , シャープ株式会社
发明人： MORI SHIGEYASU , NAKAZAWA ATSUSHI , MIYAMOTO MITSUNOBU
IPC分类号： H05K3/46 , G02F1/1368 , H01L21/336 , H01L21/768 , H01L23/12 , H01L23/522 , H01L29/786 , H05K1/11 , H05K3/40
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board that prevents a numerical aperture from decreasing by suppressing a light shield region, and facilitates manufacturing steps, and to provide a semiconductor device having the same.SOLUTION: A TFT substrate 1 includes a first insulating film 8 where a first contact hole 11 is formed, a first wiring layer 14 formed on a surface of the first insulating film 8 and a surface of the first contact hole 11, a second insulating film 9 where a second conductor hole 15 is formed, and a second wiring layer 16 laminated on the second insulating film 9, formed on a surface of the second insulating film 9 and a surface of the second contact hole 15, and electrically connecting with the first wiring layer 14. Then the first and the second contact holes 11, 15 are arranged linearly with being put one over the other in a vertical direction X of the TFT substrate 1, and the first contact hole 11 is filled with an insulating resin 25 on the first wiring layer 14.
摘要翻译：要解决的问题：提供一种通过抑制遮光区域来防止数值孔径减小的多层布线板，并且有助于制造步骤，并提供具有该多个布线板的半导体器件。解决方案：TFT基板1包括第一绝缘体形成第一接触孔11的膜8，形成在第一绝缘膜8的表面上的第一布线层14和第一接触孔11的表面，形成第二导体孔15的第二绝缘膜9，以及层叠在第二绝缘膜9上的第二布线层16，形成在第二绝缘膜9的表面和第二接触孔15的表面上，并且与第一布线层14电连接。然后，第一和第二接触孔11,15在TFT基板1的垂直方向X上彼此直线地配置，并且第一接触孔11在第一接触孔11上填充有绝缘树脂25 布线层14。

8. 发明专利

JP2008117863A Semiconductor element, and display device 审中-公开
标题翻译：半导体元件和显示器件
公开(公告)号：JP2008117863A
公开(公告)日：2008-05-22
申请号：JP2006298012
申请日：2006-11-01
申请人： Sharp Corp , シャープ株式会社
发明人： MORI SHIGEYASU , NAKAZAWA ATSUSHI , ODA AKIHIRO
IPC分类号： H01L29/786 , H01L29/41 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element and a display device which are capable of contriving the increase of ON current, the decrease of OFF current and the steepening of sub-threshold characteristics without increasing the number of processes.
SOLUTION: The semiconductor element is provided with a structure, in which a bottom gate electrode, a bottom gate insulating film, a semiconductor layer, a top gate insulating film and a top gate electrode are laminated in this sequence, while the bottom gate electrode is provided with light shielding property. When the same is seen in plan view, the semiconductor element is larger than a region in the semiconductor layer which is opposed to the top gate electrode and covers the region.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体元件和显示装置，其能够在不增加处理次数的情况下提供导通电流的增加，关断电流的减小和子阈值特性的陡峭化。解决方案：半导体元件具有这样的结构，其中底栅极电极，底栅绝缘膜，半导体层，顶栅极绝缘膜和顶栅电极以该顺序层叠，而底部栅电极具有遮光性。当在平面图中看到相同时，半导体元件大于半导体层中与顶栅电极相对并覆盖该区域的区域。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2007013055A Mask for manufacturing transistor and method for manufacturing transistor using the same 有权
标题翻译：用于制造晶体管的掩模和使用其制造晶体管的方法
公开(公告)号：JP2007013055A
公开(公告)日：2007-01-18
申请号：JP2005195219
申请日：2005-07-04
申请人： Sharp Corp , シャープ株式会社
发明人： MORI SHIGEYASU , MIYAMOTO MITSUNOBU , NAKAZAWA ATSUSHI , OKAMOTO HIROSHI
IPC分类号： H01L21/336 , G03F1/00 , G03F1/70 , H01L21/027 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To attain reduction in the number of masks and manufacturing processes in the processes for manufacturing a transistor.
SOLUTION: A mask 1 is a transistor manufacturing mask for exposing a positive resist 30 formed on an impurity containing semiconductor layer 20. A transistor to be manufactured using the mask 1 includes an intrinsic layer 20a; first conductivity type layers 20b holding the intrinsic layer 20a therebetween in a plane direction and containing impurities of higher concentration than the intrinsic layer 20a; and second conductivity type layers 20s, 20d holding the first conductivity type layers 20b therebetween in a plane direction and containing impurities of higher concentration than the first conductivity type layers 20b. The mask 1 includes a light shielding area 11 formed in an area corresponding to the second conductivity type layers 20s, 20d; a transmitting area 12 formed in an area corresponding to the first conductivity type layers 20b; and a gray tone area 13 which is formed in an area corresponding to the intrinsic layer 20a, and in which light transmissivity is higher than that in the light shielding area 11 and lower than that in the transmitting area 12.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了减少制造晶体管的工艺中的掩模和制造工艺的数量。解决方案：掩模1是用于暴露形成在含杂质的半导体层20上的正性抗蚀剂30的晶体管制造掩模。使用掩模1制造的晶体管包括本征层20a; 第一导电型层20b在平面方向上夹持本征层20a，并含有比本征层20a高的杂质; 以及在平面方向上保持第一导电类型层20b的第二导电类型层20d和20d，并且包含比第一导电类型层20b更高的浓度的杂质。掩模1包括形成在对应于第二导电类型层20s，20d的区域中的遮光区域11; 形成在与第一导电类型层20b相对应的区域中的透射区域12; 以及形成在与本征层20a相对应的区域中的透光率高于遮光区域11中的透光率低于透射区域12的灰色区域13。版权所有（C） C）2007，JPO＆INPIT

10. 发明专利

JP2006285144A Exposure device and exposure control method 审中-公开
标题翻译：曝光装置和曝光控制方法
公开(公告)号：JP2006285144A
公开(公告)日：2006-10-19
申请号：JP2005108722
申请日：2005-04-05
申请人： Sharp Corp , シャープ株式会社
发明人： MORI SHIGEYASU , MATSUO TAKUYA , MIYAMOTO MITSUNOBU
IPC分类号： G03F9/00 , G02F1/13 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide an exposure device capable of performing exposure while precisely positioning a pattern of a mask, and an exposure control method.
SOLUTION: The exposure device measures positions of a plurality of marks on a substrate (S232), stores the positions of the plurality of marks (S233), calculates deformation rates in two directions of direct axes on the substrate and a deformation rate in the direction of an axis on the substrate different from the direct axis (S234, 235) based upon positions of the plurality of marks in a current thin-film layer forming process and positions of the plurality of marks in a previous thin-film layer forming process, adds a correction value found from a parameter based upon the deformation rates of the direct axes and a parameter based upon the deformation rate in the direction of the axis different from the direct axes to coordinate values of the positions of the plurality of marks in the precious thin-film layer forming process to calculate positions of a plurality of shot regions respectively (S236), and projects patterns on the plurality of positions in order (S237, 238).
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够在精确定位掩模图案的同时进行曝光的曝光装置和曝光控制方法。曝光装置测量基板上的多个标记的位置（S232），存储多个标记的位置（S233），计算基板上直轴的两个方向的变形率和变形率在基于当前薄膜层形成处理中的多个标记的位置和基于先前薄膜层中的多个标记的位置的基于与直轴（S234,235）不同的基板上的轴的方向上基于直线轴的变形率的参数和基于与直轴不同的轴的方向上的变形率的参数，从参数中找到的校正值与多个标记的位置的坐标值相加在分别计算多个拍摄区域的位置的珍贵薄膜层形成处理中（S236），并且按顺序在多个位置上投影图案（S237,238）。版权所有（C）2007，JPO＆INPIT

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