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1. 发明专利

JP2011071521A Semiconductor device with embedded word line 有权
标题翻译：具有嵌入式字线的半导体器件
公开(公告)号：JP2011071521A
公开(公告)日：2011-04-07
申请号：JP2010214134
申请日：2010-09-24
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM HUI JUNG , OH YONG-CHUL , CHUNG HYUN WOO , KIM HYUN GI , KIM KANG UK
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10817 , H01L27/10885 , H01L29/4236
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with an embedded word line which gives high reliability, and at the same time provides a structure profitable to high integration. SOLUTION: The semiconductor device has: an element isolation film defining an active region in a substrate; a plurality of embedded word lines having an upper surface with lower level than that of the active region, surrounded by the active region, and extending to a first direction parallel to the main surface of the substrate; a gate-insulating film formed in between the embedded word line and the active region; and a plurality of embedded bit lines having the upper surface with the lower level than that of a plurality of the word lines, set in parallel to the main surface of the substrate inside it, and extending to a second direction different from the first direction. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有高可靠性的嵌入式字线的半导体器件，并且同时提供了可以高度集成的结构。解决方案：半导体器件具有：在衬底中限定有源区的元件隔离膜; 多个嵌入字线，其具有比有源区低的上表面，被有源区包围，并延伸到平行于衬底主表面的第一方向; 形成在所述嵌入字线和所述有源区之间的栅极绝缘膜; 以及多个嵌入位线，其具有比多个字线的上表面的下表面的平面高度平行于其内部的基板的主表面，并且延伸到与第一方向不同的第二方向。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2012248841A Semiconductor device including double gate electrode structure, and manufacturing method for the same 审中-公开
标题翻译：包括双门电极结构的半导体器件及其制造方法
公开(公告)号：JP2012248841A
公开(公告)日：2012-12-13
申请号：JP2012118686
申请日：2012-05-24
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM JI-YOUNG , OH YONG-CHUL , WOO DONG-SOO , CHUNG HYUN WOO , JIN GYO-YOUNG , CHOI SEONG-KWAN , HONG HYEONG-SUN , HWANG YOO-SANG
IPC分类号： H01L21/336 , H01L21/8242 , H01L21/8244 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： G11C11/4096 , G11C11/404 , G11C11/4085 , H01L21/823437 , H01L27/10823 , H01L27/10873 , H01L27/10876 , H01L27/10891 , H01L27/10894 , H01L29/41741 , H01L29/4236 , H01L29/66484 , H01L29/66613 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including a double gate electrode structure, that can increase the on current while minimizing the generation of leakage current, and provide a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device includes: a gate electrode disposed on a substrate; a first impurity implantation region and a second impurity implantation region disposed on the substrate so that each is disposed adjacent to each end of the gate electrode; and a channel region disposed between the first impurity implantation region and the second impurity implantation region. The gate electrode includes a first sub-gate electrode adjacent to the first impurity implantation region and a second sub-gate electrode adjacent to the second impurity implantation region. The first sub-gate electrode and the second sub-gate electrode are disposed on the channel region. In this semiconductor device, one channel region is independently controlled by the two sub-gates, so that the generation of leakage current can be minimized.
摘要翻译：解决的问题：提供一种包括双栅电极结构的半导体器件，其可以在使漏电流的产生最小化的同时增加导通电流，并提供半导体器件的制造方法。解决方案：半导体器件包括：设置在衬底上的栅电极; 设置在所述基板上的第一杂质注入区域和第二杂质注入区域，使得它们各自邻近所述栅极电极的每一端设置; 以及设置在第一杂质注入区和第二杂质注入区之间的沟道区。栅电极包括与第一杂质注入区相邻的第一子栅电极和与第二杂质注入区相邻的第二子栅电极。第一子栅极电极和第二子栅极电极设置在沟道区域上。在该半导体器件中，一个沟道区域由两个子栅极独立地控制，从而可以使泄漏电流的产生最小化。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2006066918A Manufacturing method of transistor equipped with gate electrode without void 审中-公开
标题翻译：带栅极电极的无晶体管的制造方法
公开(公告)号：JP2006066918A
公开(公告)日：2006-03-09
申请号：JP2005246311
申请日：2005-08-26
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： OH YONG-CHUL , KIM WOOK-JE , PARK DONG-GUN , RYO GENSHAKU
IPC分类号： H01L29/78 , H01L21/265 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L21/28035 , H01L21/28061 , H01L21/3212 , H01L21/823842
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a transistor equipped with a gate electrode without void.
SOLUTION: After forming a gate oxide film on a semiconductor substrate, a polysilicon film for a gate electrode is deposited on the upper part of the gate oxide film. Subsequently, a p-type impurity is ion-implanted into the polysilicon film, and a predetermined thickness of the polysilicon film is removed by a chemical mechanical polishing method.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种配备有无电极栅电极的晶体管的制造方法。解决方案：在半导体衬底上形成栅极氧化膜之后，在栅极氧化膜的上部沉积用于栅电极的多晶硅膜。随后，将p型杂质离子注入到多晶硅膜中，并通过化学机械抛光方法除去预定厚度的多晶硅膜。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2002033390A METHOD FOR FORMING CONDUCTIVE CONTACT BODY OF INTEGRATED CIRCUIT ELEMENT USING DUMMY INSULATING LAYER 失效
公开(公告)号：JP2002033390A
公开(公告)日：2002-01-31
申请号：JP2001165230
申请日：2001-05-31
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIN CHISHU , CHU CHANG-WOONG , KIM DONG-HYUN , OH YONG-CHUL , KIM HYOUNG-JOON , NAN HEIIN , BOKU KEIEN , LEE SANG HYEOP
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a conductive contact body for preventing electrical short-circuiting from being generated and a contact hole from being opened, and further securing an error alignment margin in a photoetching process to the high integration of a semiconductor device. SOLUTION: A number of lines that use a dummy insulating layer and are mutually isolated are included, and the dummy insulating layer is formed between portions that are selected primarily from the lines that are mutually isolated. An interlayer insulating layer is formed between one portion of the mutually isolated lines that are selected primarily, and one portion that is secondarily selected from other lines that are mutually isolated. The interlayer insulating layer has etching rate lower than the dummy insulating layer to specific etching liquid. The dummy insulating layer is etched by the specific etching liquid to remove at least one portion of the dummy insulating layer between portions that are selected primarily from the mutually isolated lines. Between portions that are selected primarily of the mutually isolated lines where at least one portion of the dummy insulating layer is removed, a conductive layer is formed, and is electrically connected to an integrated circuit between portions that are primarily selected of the mutually isolated lines.

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