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1. 发明专利

JP2006261708A Semiconductor memory device having self-aligning contact and its manufacturing method 审中-公开
标题翻译：具有自我调节接触器的半导体存储器件及其制造方法
公开(公告)号：JP2006261708A
公开(公告)日：2006-09-28
申请号：JP2006185917
申请日：2006-07-05
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM MYEONG-CHEOL , NAN HEIIN , JEONG SANG-SUP , AHN TAE-HYUK
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/28 , H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device having self-aligning contact and its manufacturing method.
SOLUTION: After a first insulating substrate 23 is formed on a semiconductor substrate 1 on which a gate electrode (parallel to the drawing, but not shown) is formed, at least one or more first openings (parallel to the drawing, but not shown) and at least one or more second openings 25b for exposing the activation area 21 of the semiconductor substrate 1 are formed, and a first pad layer (not shown) and a second pad layer 25b' are formed by filling each opening with a conductive material. After a first interlayer insulating film 27 is formed on the first insulating film 23, a third opening (not shown) is formed, and insulating spacers 33 are formed only on the both side walls by forming a plurality of bit lines 29 in a direction perpendicular to the gate electrode, while filling the third opening. After a second interlayer insulating film 35 is formed, by causing the second interlayer insulating film 35 to self-align with the bit lines 29 and the insulating spacer 33, a fourth opening 37 for exposing the surface of the second pad layer 25b' is formed, and by filling the opening 37 with a conductive material, a storage electrode 39 is formed thereon.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有自对准接触的半导体存储器件及其制造方法。解决方案：在第一绝缘基板23形成在其上形成栅电极（平行于图，但未示出）的半导体基板1上的至少一个或多个第一开口（平行于图，但是形成用于露出半导体衬底1的激活区域21的至少一个或多个第二开口25b，并且通过将每个开口填充到第一衬垫层（未示出）和第二衬垫层25b' 导电材料。在第一绝缘膜23上形成第一层间绝缘膜27之后，形成第三开口（未示出），并且通过在垂直方向上形成多个位线29而仅在两个侧壁上形成绝缘间隔物33 同时填充第三个开口。在形成第二层间绝缘膜35之后，通过使第二层间绝缘膜35与位线29和绝缘间隔物33自对准，形成用于暴露第二焊盘层25b'的表面的第四开口37 并且通过用导电材料填充开口37，在其上形成存储电极39。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006060220A Method for forming capacitor of semiconductor device 有权
标题翻译：形成半导体器件电容器的方法
公开(公告)号：JP2006060220A
公开(公告)日：2006-03-02
申请号：JP2005236153
申请日：2005-08-16
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHO SEONG-IL , KIN SHOKEI , NAN HEIIN , CHI KYOKYU , LEE CHEOL-KYU
IPC分类号： H01L21/8242 , H01L21/3065 , H01L21/768 , H01L21/8246 , H01L27/105 , H01L27/108
CPC分类号： H01L28/60 , H01L21/32136 , H01L21/32139 , H01L27/10852 , H01L27/11502 , H01L27/11507
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a capacitor of a semiconductor device.
SOLUTION: This method comprises a step for forming a capacitor electrode by etching a metal nitride film under an environment containing fluorine and oxygen. The metal nitride film may be plasma-etched under an environment containing fluorine plasma. The fluorine may consist of at least one of CF
4 and CHF
3 . Further, the metal nitride film may comprise at least one out of titanium, tantalum and tungsten. The metal nitride film may be plasma-etched under an environment where a power of 600 W or less is supplied.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种形成半导体器件的电容器的方法。解决方案：该方法包括通过在包含氟和氧的环境下蚀刻金属氮化物膜来形成电容器电极的步骤。金属氮化物膜可以在含有氟等离子体的环境下进行等离子体蚀刻。氟可以由CF 4 和CHF 3 中的至少一种组成。此外，金属氮化物膜可以包括钛，钽和钨中的至少一种。可以在供给600W以下的功率的环境下等离子体蚀刻金属氮化物膜。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005340840A Method of manufacturing recess channel mosfet 有权
标题翻译：制造通道MOSFET的方法
公开(公告)号：JP2005340840A
公开(公告)日：2005-12-08
申请号：JP2005157965
申请日：2005-05-30
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHUNG SUNG-HOON , NAN HEIIN , CHI KYOKYU
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8234 , H01L21/8242
CPC分类号： H01L29/66621 , H01L21/823412 , H01L21/823437 , H01L27/10876
摘要： PROBLEM TO BE SOLVED: To provide the method of manufacturing a recess channel MOSFET capable of forming a recess trench without cutting a recess in the portion of the element isolation film of a substrate.
SOLUTION: In the method of manufacturing a recess channel MOSFET, an insulating film pattern is formed on a semiconductor substrate 110. Then, a silicon oxide film is deposited on it. The insulating film pattern is removed by planarizing the silicon oxide film using the insulating film pattern as a planarization ending point and thereby forming a silicon oxide film mask pattern between the insulating film patterns. A recess trench 145 is formed by etching the substrate using the silicon oxide film mask pattern 142 as an etching mask. This method provides the effect of removing the recess formed in the substrate at the time of the deposition of the silicon oxide film.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供制造能够形成凹槽而不切割衬底的元件隔离膜的部分中的凹部的凹槽通道MOSFET的方法。解决方案：在制造凹槽沟道MOSFET的方法中，在半导体衬底110上形成绝缘膜图案。然后，在其上沉积氧化硅膜。通过使用绝缘膜图案作为平坦化终点平面化氧化硅膜，从而在绝缘膜图案之间形成氧化硅膜掩模图案来除去绝缘膜图案。通过使用氧化硅膜掩模图案142作为蚀刻掩模蚀刻衬底来形成凹槽145。该方法提供了在沉积氧化硅膜时去除在基板中形成的凹部的效果。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2001196456A SEMICONDUCTOR ELEMENT HAVING SELF-ALIGNED CONTACT AND METHOD OF MANUFACTURING THE SAME 失效
公开(公告)号：JP2001196456A
公开(公告)日：2001-07-19
申请号：JP2000363608
申请日：2000-11-29
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM MYEONG-CHEOL , NAN HEIIN , BIN KOCHIN , AHN TAE-HYUK
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element having a self-aligned contact with which the parasitic capacitance between the conductive contact and a conductive layer can be minimized. SOLUTION: The semiconductor element contains a plurality of mutually adjoining conductive-layer patterns formed by sequentially stacking and patterning a first conductive layer 4 and a mask layer 6 on a specified underlying layer, a first insulating film 8 that fills the space between the conductive- layer patterns while parts of the upper side of the conductive-layer patterns are exposed, second insulating films 10 having a spacer shape formed on side walls of the conductive-layer patterns that are exposed over the first insulating film 8, and a second conductive layer 16 self-aligned to the second insulating films 10 located between the adjoining conductive-layer patterns and simultaneously filled in a contact hole that penetrates the first insulating film 8.

5. 发明专利

JP2002280452A INTEGRATED CIRCUIT DEVICE PREVENTING SHORT CIRCUIT EFFECTIVELY AND ITS FABRICATING METHOD 审中-公开
公开(公告)号：JP2002280452A
公开(公告)日：2002-09-27
申请号：JP2002009100
申请日：2002-01-17
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM HYOUNG-JOON , PARK YOUNG-WOOK , NAN HEIIN
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit device comprising a microelectronic substrate and a conductive layer formed thereon. SOLUTION: The integrated circuit device comprises a microelectronic substrate 100, a conductive layer 107 formed thereon, an insulation layer 108 formed on the conductive layer 107 and including a protrusion extending above the conductive layer 107, and a side wall insulating region 110a provided on the side face of the conductive layer 107 contiguously to one side wall thereof and extending between the protrusion of the insulation layer 108 and the microelectronic substrate 100.

6. 发明专利

JP2002033390A METHOD FOR FORMING CONDUCTIVE CONTACT BODY OF INTEGRATED CIRCUIT ELEMENT USING DUMMY INSULATING LAYER 失效
公开(公告)号：JP2002033390A
公开(公告)日：2002-01-31
申请号：JP2001165230
申请日：2001-05-31
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIN CHISHU , CHU CHANG-WOONG , KIM DONG-HYUN , OH YONG-CHUL , KIM HYOUNG-JOON , NAN HEIIN , BOKU KEIEN , LEE SANG HYEOP
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a conductive contact body for preventing electrical short-circuiting from being generated and a contact hole from being opened, and further securing an error alignment margin in a photoetching process to the high integration of a semiconductor device. SOLUTION: A number of lines that use a dummy insulating layer and are mutually isolated are included, and the dummy insulating layer is formed between portions that are selected primarily from the lines that are mutually isolated. An interlayer insulating layer is formed between one portion of the mutually isolated lines that are selected primarily, and one portion that is secondarily selected from other lines that are mutually isolated. The interlayer insulating layer has etching rate lower than the dummy insulating layer to specific etching liquid. The dummy insulating layer is etched by the specific etching liquid to remove at least one portion of the dummy insulating layer between portions that are selected primarily from the mutually isolated lines. Between portions that are selected primarily of the mutually isolated lines where at least one portion of the dummy insulating layer is removed, a conductive layer is formed, and is electrically connected to an integrated circuit between portions that are primarily selected of the mutually isolated lines.

7. 发明专利

JP2001102550A SEMICONDUCTOR MEMORY HAVING SELF-ALIGNED CONTACT AND MANUFACTURING METHOD THEREFOR 失效
公开(公告)号：JP2001102550A
公开(公告)日：2001-04-13
申请号：JP2000265869
申请日：2000-09-01
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM MYEONG-CHEOL , NAN HEIIN , JEONG SANG-SUP , AHN TAE-HYUK
IPC分类号： H01L21/8242 , H01L21/60 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory having self-aligned contact and its manufacturing method. SOLUTION: After forming a first insulation film 23 on a semiconductor substrate 1 having a gate electrode, at least one first opening and at least one second opening 25b', from which an active region 21 of the semiconductor substrate 1 is exposed, are formed. Each opening is filled with a conductive material to form a first pad layer and a second pad layer 25b'. After forming a fist interlayer insulation film 27 on the first insulation layer 23, a third opening from which the surface of the first pad layer is exposed, is formed and filled, and at the same time, several bit lines 29 orthogonal to the gate electrode are formed, and an insulation spacer 33 is provided only to each of their sidewalls. After forming a second interlayer insulation film 35, a fourth opening 37, which is self-adjusted to the insulation spacers 33 and exposes the surface of the second pad layer 25b', is formed and filled with a conductive material, on which a storage electrode 39 is formed.

8. 发明专利

JP2004080045A Method for etching metal film with mask, method for forming wiring of semiconductor device, method for etching metal film and etching gas 审中-公开
公开(公告)号：JP2004080045A
公开(公告)日：2004-03-11
申请号：JP2003295659
申请日：2003-08-19
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： SON SEUNG-YOUNG , LEE CHEOL-KYU , KANG CHANG-JIN , NAN HEIIN
IPC分类号： H01L21/28 , C23F4/00 , H01L21/3065 , H01L21/3205 , H01L21/3213 , H01L23/52
CPC分类号： C23F4/00 , H01L21/32136 , H01L21/32139
摘要： PROBLEM TO BE SOLVED: To provide a method for etching an Al wiring layer employing an etching gas in which N
2 gas is a main component and a method for forming wiring of a semiconductor device by the above method.
SOLUTION: In the method, an Al film is formed on a semiconductor substrate, then, a hard mask pattern to expose a part of the Al film is formed on the Al film. The exposed Al film is etched using an etching gas in which a Cl
2 gas and an N
2 gas are mixed at a flow ratio of 1/1 to 1/10.
COPYRIGHT: (C)2004,JPO

9. 发明专利

JPH11214369A PLATINUM FILM ETCHING METHOD FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH11214369A
公开(公告)日：1999-08-06
申请号：JP22838498
申请日：1998-08-12
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： NAN HEIIN , SHU HEIZEN
IPC分类号： C23F4/00 , H01L21/02 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/3213
摘要： PROBLEM TO BE SOLVED: To provide an etching method for obtaining a platinum pattern in which for remainder is left, an etching speed is increased, and an etching inclination is sharp at platinum film etching of a semiconductor device. SOLUTION: A mask layer is formed on a platinum film formed on a semiconductor substrate. A pohotoresist pattern 15 is formed on a mask layer, and the mask layer is plasma-etched by using this as a mask so that a mask pattern 13a is formed. Then, a platinum film is plasma-etched by using the photoresist pattern and the mask pattern as a mask, so that a platinum pattern 11a can be formed. At this time, a platinum byproduct 17 is formed at both sidewalls of the photoresist pattern. The plasma etching of the platinum film is operated by using Ar, Ar/Cl2 , or Ar/HBr gas. The platinum byproduct and the mask pattern from which the photo resist pattern is removed is plasma-etched and removed through using Cl2 /O2 or HBr/O2 gas.

10. 发明专利

JP2002026293A SEMICONDUCTOR MEMORY ELEMENT HAVING SELF-ALIGNED CONTACT AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002026293A
公开(公告)日：2002-01-25
申请号：JP2001098868
申请日：2001-03-30
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： AHN TAE-HYUK , KIM MYEONG-CHEOL , RI JUGEN , NAN HEIIN , BIN KOCHIN
IPC分类号： H01L27/10 , H01L21/60 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide self-aligned contacts which are improved in process margin by preventing the occurrence of short circuits between contacts for bit lines and contacts for storage electrodes. SOLUTION: The occurrence of short circuits between contacts 25 for bit lines and contacts 35 for storage electrodes can be prevented through a simple process by simultaneously self-aligning the contacts with bit lines 27 and spacers formed on the side walls of a gate electrode pattern 17. When the contacts 35 are formed, in addition, the misalignment margin is increased in a photographic process for forming the contacts 35 by arranging the contacts 35 zigzag so that the contacts 35 may be deviated as much as possible to the outside of each active area. Moreover, when starting CMP or etch back in a state where a conductive film is vapor deposited on the whole surface after the contacts 25 are formed, the contacts 25 are etched to the heights of mask layers.

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