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1. 发明专利

JP2008123479A Simd (single instruction multiple data) and memory array structure for the same 审中-公开
标题翻译： SIMD（单指令多数据）和存储器阵列结构
公开(公告)号：JP2008123479A
公开(公告)日：2008-05-29
申请号：JP2007115850
申请日：2007-04-25
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： BOKU KIGO , BOKU SEIBAI , KIM SHIN-DUG , PARK JUNG-WOOK , PARK JOON KYU
IPC分类号： G06F15/80 , G06F9/38 , G06F12/06
CPC分类号： G06F15/8015
摘要： PROBLEM TO BE SOLVED: To provide an SIMD and a memory array structure for the SIMD.
SOLUTION: A single instruction multiple data processor (SIMD) includes a plurality of operation elements for executing parallel operations with input data, a memory for rearranging and storing the data to enable collision avoidance access for a memory access pattern required by a video codec, and a data interconnection unit for performing predetermined bit-shifting of a plurality of data output from the memory and providing a corresponding operation element with the plurality of data upon data access from the operation elements.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为SIMD提供SIMD和存储器阵列结构。解决方案：单指令多数据处理器（SIMD）包括用于执行与输入数据的并行操作的多个操作元件，用于重新排列和存储数据的存储器，以使视频所需的存储器访问模式能够进行冲突避免访问编解码器和数据互连单元，用于执行从存储器输出的多个数据的预定位移位，并且在从操作元件进行数据访问时向多个数据提供相应的操作元素。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2005057768A Delay clock signal generating device and delay clock signal generating method 有权
标题翻译：延迟时钟信号发生装置和延迟时钟信号发生方法
公开(公告)号：JP2005057768A
公开(公告)日：2005-03-03
申请号：JP2004225944
申请日：2004-08-02
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： JUNG GUN-OK , KIM CHINKAN , BOKU SEIBAI , KIM CHUL-WOO , YOON SEOK-SOO , YOON SEOK-RYOUNG
IPC分类号： G06F1/06 , H03H11/26 , H03K5/00 , H03K5/05 , H03K5/13 , H03K5/135 , H03K5/15 , H03K5/26 , H03L7/081 , H04L7/02
CPC分类号： H03K5/133 , H03K5/135 , H03K2005/00156 , H03K2005/00286
摘要： PROBLEM TO BE SOLVED: To provide a delay clock signal generating device which detects a half cycle of a clock signal and has a predetermined phase difference different from the clock signal, and a method therefor. SOLUTION: A delay clock signal generating device includes a clock signal generating circuit which generates a clock signal clk, a delay signal generating circuit which generates a plurality of delay signals delayed by the clock signal clk, a phase detecting circuit which detects a signal delayed by a half cycle (π) from the clock signal and generates a selection signal, a phase interpolating circuit which adjusts a minute delay time of a delay signal, and a selection circuit which outputs a signal delayed by a predetermined phase from the clock signal by the selection signal. A clock signal delayed by a desired amount such as π/2 or 3π/2 from the clock signal can be obtained. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种检测时钟信号的半周期并具有与时钟信号不同的预定相位差的延迟时钟信号发生装置及其方法。解决方案：延迟时钟信号发生装置包括产生时钟信号clk的时钟信号产生电路，产生延迟时钟信号clk的多个延迟信号的延迟信号产生电路，相位检测电路，信号从时钟信号延迟半周期（π）并产生选择信号，调整延迟信号的微小延迟时间的相位内插电路以及从时钟输出延迟预定相位的信号的选择电路信号由选择信号。可以获得从时钟信号延迟所需量（例如π/ 2或3π/ 2）的时钟信号。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2004242317A Frequency multiplier and multiplication method for adjusting duty cycle of clock 有权
公开(公告)号：JP2004242317A
公开(公告)日：2004-08-26
申请号：JP2004027879
申请日：2004-02-04
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： JUNG GUN-OK , BOKU SEIBAI
IPC分类号： G06F1/06 , G01R25/04 , G06F7/68 , G11C11/407 , G11C11/4076 , H03B19/00 , H03K5/00 , H03K5/04 , H03K5/13 , H03K5/156 , H03L7/081
CPC分类号： H03K5/00006 , G06F7/68 , H03K5/1565 , H03L7/0814
摘要： PROBLEM TO BE SOLVED: To provide a frequency multiplier and multiplication method with which a duty cycle of a clock can be adjusted. SOLUTION: The frequency multiplier is equipped with a delay circuit for receiving a first clock to output a delay clock resulting from delaying the first clock for a predetermined time, an exclusive OR means for receiving the first clock and the delay clock to output a second clock resulting from exclusively ORing the first clock and the delay clock, and a control circuit for detecting a phase difference between the first clock and the delay clock and outputting a predetermined control signal corresponding to the detected phase difference to the delay circuit, and the control signal controls a delay quantity in the delay circuit. The delay quantity in the delay circuit is adjusted in response to the control signal, so that the frequency multiplier can automatically adjust the duty cycle of the clock to be multiplied. COPYRIGHT: (C)2004,JPO&NCIPI

4. 发明专利

JP2004103012A Cache structure for enhancing operating speed of processor and processor having cache management method 审中-公开
标题翻译：用于提高处理器操作速度的缓存结构和具有缓存管理方法的处理器
公开(公告)号：JP2004103012A
公开(公告)日：2004-04-02
申请号：JP2003304649
申请日：2003-08-28
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： BOKU SEIBAI
IPC分类号： G06F9/32 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3802 , G06F9/3861 , G06F12/0848
摘要： PROBLEM TO BE SOLVED: To provide a processor having cache structure for enhancing operating speed of the processor and a cache management method.
SOLUTION: The processor is provided with a cache memory and an instruction word register. It is also provided with (a) a stage for dividing the cache memory into a cache for normal program and a cache for exception program, (b) a stage for storing an instruction word and/or data for execution of the normal program in the cache for normal program and for storing an instruction word and/or data for execution of the exception program in the cache for exception program and (c) a stage for deciding whether the processor executes the normal program or the exception program, for fetching the instruction word from any one of the cache for normal program and the cache for exception program and inputting the instruction word in the instruction word register.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供具有用于提高处理器的操作速度的高速缓存结构的处理器和高速缓存管理方法。解决方案：处理器配有高速缓冲存储器和指令字寄存器。还提供了（a）用于将高速缓冲存储器划分为用于正常程序的高速缓存和用于异常程序的高速缓存的阶段，（b）用于存储用于执行正常程序的指令字和/或数据的级用于正常程序的缓存和用于在用于异常程序的高速缓存中存储用于执行异常程序的指令字和/或数据的缓存，以及（c）用于判定处理器是否执行正常程序或异常程序的级，用于获取指令来自正常程序的缓存中的任何一个字和用于异常程序的缓存，并在指令字寄存器中输入指令字。版权所有（C）2004，JPO

5. 发明专利

JP2002083975A SOI FIELD-EFFECT TRANSISTOR CONTAINING BODY CONTACTING SECTION FOR REMOVING FLOATING BODY EFFECT AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2002083975A
公开(公告)日：2002-03-22
申请号：JP2001232469
申请日：2001-07-31
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： BOKU SEIBAI , KIM JUN , KIM EUN HAN , KYO HIISEI , KIM YOUNG-WUG
IPC分类号： H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide an SOI field-effect transistor which does not generate such a capacitance that decreases the speed of the transistor in a contacting section and which can reduce floating body effects even when the transistor is not provided with additional metallic wiring for supplying electric power to a body, and a method of manufacturing the transistor. SOLUTION: A body contacting section is formed by forming a trench to a semiconductor substrate through the body and a buried oxide film and filling up the trench with a conductive filler for obtaining electrical connection between the body and semiconductor substrate. In a prescribed region of the semiconductor substrate which is in contact with the lower part of the body contacting section, an ohmic contact region is formed by implanting the ion of an impurity into the region. Consequently, the used area is reduced, because no metallic wiring is added for supplying electric power to the body. In addition, the abnormal operation of a circuit due to the capacitance generated in a contacting section can also be prevented.

6. 发明专利

JP2001168337A SOI SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001168337A
公开(公告)日：2001-06-22
申请号：JP2000323881
申请日：2000-10-24
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM YOUNG-WUG , KIN HEIZEN , KYO HIISEI , KO YONKEN , BOKU SEIBAI
IPC分类号： H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a technique which can be applied to a commercial SOI product and which is used to remove a floating body effect in an SOI MOS transistor. SOLUTION: A transistor active region 1a, a body line 1b which is arranged on one side of it, and a body extension part 1e which is situated between both, are formed on an SOI substrate. The body region of the transistor active region 1b (the SOI MOS transistor) is connected electrically to the body line 1b connected to a ground line or a power-supply line 9 via the body extension part 1e.

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