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1. 发明专利

JP2002043328A MOS FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2002043328A
公开(公告)日：2002-02-08
申请号：JP2001123229
申请日：2001-04-20
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YANG JEONG-HWAN , KIM YOUNG-WUG
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a MOS field effect transistor with a reduced resistance between a source and a drain. SOLUTION: A gate insulating film 210 and a gate electrode 220 are formed successively on a semiconductor substrate 200. Then a deep source/drain region 230 is formed in the upper region of the semiconductor substrate outside the side wall of the gate electrode. Then an extending source/drain region 240 thinner than the deep source/drain region and extending toward a channel region under the gate electrode is formed in the upper region of the semiconductor substrate. Then a 1st silicide layer 261 with a 1st thickness is formed in the upper surface of the deep source/drain region, and a 2nd silicide layer 262 extending from the 1st silicide layer but with a 2nd thickness thinner than the 1st thickness of the 1st silicide layer is formed in a part of the surface part of the upper part of the extending source/drain region.

2. 发明专利

JP2002083975A SOI FIELD-EFFECT TRANSISTOR CONTAINING BODY CONTACTING SECTION FOR REMOVING FLOATING BODY EFFECT AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2002083975A
公开(公告)日：2002-03-22
申请号：JP2001232469
申请日：2001-07-31
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： BOKU SEIBAI , KIM JUN , KIM EUN HAN , KYO HIISEI , KIM YOUNG-WUG
IPC分类号： H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide an SOI field-effect transistor which does not generate such a capacitance that decreases the speed of the transistor in a contacting section and which can reduce floating body effects even when the transistor is not provided with additional metallic wiring for supplying electric power to a body, and a method of manufacturing the transistor. SOLUTION: A body contacting section is formed by forming a trench to a semiconductor substrate through the body and a buried oxide film and filling up the trench with a conductive filler for obtaining electrical connection between the body and semiconductor substrate. In a prescribed region of the semiconductor substrate which is in contact with the lower part of the body contacting section, an ohmic contact region is formed by implanting the ion of an impurity into the region. Consequently, the used area is reduced, because no metallic wiring is added for supplying electric power to the body. In addition, the abnormal operation of a circuit due to the capacitance generated in a contacting section can also be prevented.

3. 发明专利

JP2001118997A SEMICONDUCTOR ELEMENT HAVING SOI STRUCTURE AND MANUFACTURING METHOD THEREFOR 失效
公开(公告)号：JP2001118997A
公开(公告)日：2001-04-27
申请号：JP2000147113
申请日：2000-05-18
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KO EIKEN , KIN HEIZEN , KIM YOUNG-WUG
IPC分类号： H01L21/28 , H01L21/00 , H01L21/329 , H01L21/336 , H01L21/762 , H01L21/822 , H01L21/8234 , H01L21/84 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/76 , H01L29/786 , H01L29/868 , H01L29/96 , H01L31/0392 , H01L31/062 , H01L31/113
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element having an SOI structure, where the occurrence of junction leakage current appearing on the side of a diffusion region used as a diode or well resistance element is minimized and the operation characteristic of the semiconductor element is improved, and to provide its manufacturing method. SOLUTION: Diffusion regions 2 and 1 are made to be duplex junction structures which differ in concentration gradient by using a spacer 124a, for example a structure where a P-layer 120 surrounds a P+layer 134 or structure where N-layer 114 surrounds an N+layer 128. A silicide layer 138 is formed only on the surface of a heavily-doped layer, namely, the P+layer 134 or the N+layer 128. Thus, the distance from the side of the silicide layer 138 to the side of the diffusion regions 2 and 1 is secured fully.

4. 发明专利

JP2005197676A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005197676A
公开(公告)日：2005-07-21
申请号：JP2004360424
申请日：2004-12-13
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： KIM YOUNG-WUG , MAEDA SHIGENOBU
IPC分类号： H01L21/76 , H01L21/336 , H01L21/84 , H01L29/78 , H01L29/786
CPC分类号： H01L29/785 , H01L21/84 , H01L29/66621 , H01L29/66772 , H01L29/66795 , H01L29/7842 , H01L29/78645
摘要： PROBLEM TO BE SOLVED: To disclose a semiconductor device overcoming a structural instability caused by silicidation and a manufacturing method thereof. SOLUTION: After a substrate containing an active area defined by an element separation film is manufactured, an etching mask containing a silicidation preventive pattern that exposes a part of the active areas on the element separation film and the active areas is formed. Afterwards, a gate structure is formed on an exposed active area, a sidewall spacer is formed on the sidewall of the gate structure on the silicidation preventive pattern. Afterwards, the manufacturing method of the semiconductor device that forms source/drain areas on the active areas with the sidewall spacer as a mask and the semiconductor device thereby are provided. Voids or a structural intrusion caused when the source/drain of a transistor is silicidated can be prevented. Therefore, the method is reliable, and easily manufactures the transistor with excellent operating characteristics. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：公开一种克服由硅化物引起的结构不稳定性的半导体器件及其制造方法。解决方案：在制造含有由元件分离膜限定的有源区的基板之后，形成包含暴露元件分离膜上的一部分有源区和有源区的防硅图案的蚀刻掩模。之后，在暴露的有源区域上形成栅极结构，在硅化防止图案上的栅极结构的侧壁上形成侧壁间隔物。此后，提供了以有侧壁间隔物作为掩模的有源区域形成源极/漏极区域的半导体器件的制造方法及其半导体器件。可以防止当晶体管的源极/漏极被硅化时引起的空穴或结构入侵。因此，该方法可靠，并且容易制造具有优异操作特性的晶体管。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JPH11214327A FORMING METHOD OF SILICIDE USING COBALT/NIOBIUM DOUBLE METALLIC STRUCTURE 失效
公开(公告)号：JPH11214327A
公开(公告)日：1999-08-06
申请号：JP30918198
申请日：1998-10-29
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： RI SHOBU , KEN NEISAI , BAE DAIROKU , KIM YOUNG-WUG
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To prevent reaction between a silicide film in a source/drain region and an upper wiring layer in an MOS transistor by concurrently forming an upper part of a gate electrode and the silicide film. SOLUTION: An Nb film 24 with a higher oxidizable characteristic than a silicon substrate, and a Co film 25 with a diffusion coefficient relatively larger than those of the Nb film 24 and the silicon substrate are formed sequentially on the silicon substrate to form a Co/Nb double metal layer. Then a heat treatment step is carried out for the double metal layer to form a Co silicide film in a reverse state and a Co/Nb metal alloy layer 29 formed thereon.

6. 发明专利

JP2007258758A Manufacturing method of capacitor for analog functions 有权
标题翻译：用于模拟功能的电容器的制造方法
公开(公告)号：JP2007258758A
公开(公告)日：2007-10-04
申请号：JP2007175703
申请日：2007-07-04
申请人： Samsung Electronics Co Ltd , サムスンエレクトロニクスカンパニーリミテッド
发明人： OH CHANG-BONG , KIM YOUNG-WUG
IPC分类号： H01L21/822 , H01L27/04 , H01L21/02 , H01L21/8234 , H01L27/06
CPC分类号： H01L28/60
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a capacitor which prevents constituents except an upper electrode 112 of the capacitor from being affected by a doping agent during doping and makes the upper and lower electrodes 112 and 106a of the capacitor have a sufficient doping level and almost the same doping concentration each other.
SOLUTION: After being polished by means of CMP, the upper surface of the upper electrode 112 of the capacitor is doped by the same doping process as that of the lower electrode 106a of the capacitor. After the lower electrode 106a of the capacitor is formed, a thermal oxidation process is performed so that impurity ions implanted into the lower electrode 106a of the capacitor are isolated on the upper surface of the lower electrode of the capacitor. This causes the upper and lower electrodes of the capacitor to have almost the same doping concentration at the interface between them.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供电容器的制造方法，其防止在掺杂期间除了电容器的上电极112以外的成分受掺杂剂的影响，并且使得电容器的上电极112和下电极106a具有充分的掺杂水平和几乎相同的掺杂浓度。解决方案：通过CMP抛光后，电容器的上电极112的上表面通过与电容器的下电极106a相同的掺杂工艺被掺杂。在形成电容器的下电极106a之后，进行热氧化处理，使得注入到电容器的下电极106a中的杂质离子被隔离在电容器的下电极的上表面上。这使得电容器的上电极和下电极在它们之间的界面处具有几乎相同的掺杂浓度。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2004104128A Sram device formed on soi substrate 有权
公开(公告)号：JP2004104128A
公开(公告)日：2004-04-02
申请号：JP2003311955
申请日：2003-09-03
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： GO SHOHO , KIM YOUNG-WUG
IPC分类号： H01L27/08 , G11C11/412 , H01L21/8238 , H01L21/8244 , H01L21/84 , H01L27/092 , H01L27/11 , H01L27/12 , H01L29/786
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1104 , H01L27/1203 , Y10S257/903
摘要： PROBLEM TO BE SOLVED: To provide an SRAM device, which reduces the whole chip size, while enabling improvement in mobility and operating characteristics of a PMOS transistor.
SOLUTION: This SRAM device is formed on an SOI substrate comprising a first active region and a second active region. In each region, a first inverter, which consists of an NMOS transistor for a first access, an NMOS transistor for a first drive, and a PMOS transistor for a first load, and a second inverter, which consists of an NMOS transistor for a second access, an NMOS transistor for a second drive, and a PMOS transistor for a second load are formed. In the channels of the PMOS transistor for the first load and that for the second load, migration directions of the carriers are extended in the silicon crystal growth direction [110]. The drains of the NMOS transistors for accessing, those of the NMOS transistors for driving, and those of the PMOS transistor for loading are contacted in common.
COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2003318258A Forming method of dual damascene wiring using low permeability insulating film 有权
标题翻译：使用低渗透性绝缘膜的双面接线的成型方法
公开(公告)号：JP2003318258A
公开(公告)日：2003-11-07
申请号：JP2003109503
申请日：2003-04-14
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： KIM SHINGEN , KIM YOUNG-WUG , PARK TAE-SOO , LEE KYUNG-TAE
IPC分类号： H01L21/28 , H01L21/311 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L23/53295 , H01L21/31116 , H01L21/312 , H01L21/3121 , H01L21/3127 , H01L21/31629 , H01L21/31633 , H01L21/3185 , H01L21/76807 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a forming method of dual damascene wiring. SOLUTION: In this forming method of dual damascene wiring, a low permeability low-k organic polymer is used as an insulating film. Only one hard mask 325 is used, a self-aligned spacer 340, and the hard mask 325 and an etching preventing film 315 which are different in an etching rate are used, and the insulating film composed of organic polymer is not damaged by ashing. A viahole smaller than a limit size can be formed by a photolithography process. Since only the one hard mask 325 is used, the process is simple. The forming method of the dual damascene wiring free from a sensitized film tail can be provided. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供双镶嵌布线的成形方法。解决方案：在这种双镶嵌布线的形成方法中，使用低磁导率低k有机聚合物作为绝缘膜。仅使用一个硬掩模325，自对准间隔物340，以及蚀刻速率不同的硬掩模325和防蚀膜315，并且由有机聚合物构成的绝缘膜不被灰化而损坏。可以通过光刻工艺形成小于极限尺寸的通孔。由于仅使用一个硬掩模325，因此该过程简单。可以提供没有敏化膜尾部的双镶嵌布线的形成方法。版权所有（C）2004，JPO

9. 发明专利

JPH11297830A SEMICONDUCTOR ELEMENT AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11297830A
公开(公告)日：1999-10-29
申请号：JP29312598
申请日：1998-10-15
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： RI KYOTAI , KIM YOUNG-WUG
IPC分类号： H01L23/52 , H01L21/28 , H01L21/3205 , H01L21/322 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To remove a defective process, which is generated at the time of the formation of microscopic contact holes or via holes, to contrive the high integration of a semiconductor element and an increase in the performance of the element. SOLUTION: First interlayer insulating films 210 are formed on a semiconductor substrate S, first contact holes h1 are formed in these films 210 and after these holes h1 are filled with first conductive plugs 214, second interlayer insulating films 216 are formed on the films 210. Moreover, second contact holes h2 are formed in these films 216 in succession to the holes h1, these holes h2 are filled with second conductive plugs 218, and contact hole parts are made to complete.

10. 发明专利

JP2003318283A Semiconductor element using silicon germanium gate and method for manufacturing the same 有权
标题翻译：使用硅锗门的半导体元件及其制造方法
公开(公告)号：JP2003318283A
公开(公告)日：2003-11-07
申请号：JP2003080765
申请日：2003-03-24
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： RYU HYUK-JU , KIM YOUNG-WUG , GO SHOHO , KANG HEE-SUNG
IPC分类号： H01L21/28 , H01L21/306 , H01L21/3065 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L27/092 , H01L21/823842
摘要： PROBLEM TO BE SOLVED: To provide a CMOS semiconductor element using a silicon germanium gate and a method for manufacturing it.
SOLUTION: A gate insulating film, a conductive electrode film with selective film quality, a silicon germanium electrode film and a conductive amorphous electrode film are successively formed on a semiconductor substrate so that a silicon germanium electrode film can be formed only in a PMOS area, and not formed in an NMOS area. Afterwards, the silicon germanium electrode film in the NMOS area is removed through a photo-etching process, and the silicon germanium electrode film is made to remain only in the PMOS area.
COPYRIGHT: (C)2004,JPO

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