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1. 发明专利

JPH0561566B2 失效
公开(公告)号：JPH0561566B2
公开(公告)日：1993-09-06
申请号：JP21079990
申请日：1990-08-08
申请人： SONY TEKTRONIX CORP
发明人： SAKAMOTO ATSUSHI
IPC分类号： G01R13/20 , G01D7/00 , G01R13/28 , G09G5/36

2. 发明专利

JPS63292376A IMAGE MEMORY DEVICE 失效
公开(公告)号：JPS63292376A
公开(公告)日：1988-11-29
申请号：JP12899587
申请日：1987-05-26
申请人： SONY TEKTRONIX CORP
发明人： SAKAMOTO ATSUSHI
IPC分类号： G06F12/00 , G06F12/06 , G06T11/00
摘要： PURPOSE:To increase a writing speed in an image memory by dividing a display area and allocating the image elements of each divided area to combinations of memory controllers and image memories. CONSTITUTION:Image element address signals received from image element information generating means 30, 32 and 34 are divided into higher and lower level bits. A decoder 46 selects the combinations of memory controllers 48 and image memories 50 in response to low-order bits. The high-order bits of an image element address and image element data are stored in a selected controller 48. Thus the address of the corresponding memory 50 is immediately designated by the high-order bits of an image element address signal and the image element data is stored in said address. Those image element address signal produced by the means 30, 32 and 34 show the coordinates of the vectors to be displayed and therefore the address signals of the same contents are never produced continuously. Thus it is possible to store the image element data signals into the corresponding picture memories while other plural memory controllers are accessed. Then the data can be written at a high speed into a low-speed and large-capacity image memory.

3. 发明专利

JPS6310189A VERTICAL CURSOR DATA GENERATION CIRCUIT FOR RASTER SCAN DISPLAY UNIT 失效
公开(公告)号：JPS6310189A
公开(公告)日：1988-01-16
申请号：JP15473286
申请日：1986-07-01
申请人： SONY TEKTRONIX CORP
发明人： SAKAMOTO ATSUSHI
IPC分类号： G09G5/08 , G09G1/06

4. 发明专利

JPS6137810B2 失效
公开(公告)号：JPS6137810B2
公开(公告)日：1986-08-26
申请号：JP1780580
申请日：1980-02-18
申请人： SONY TEKTRONIX CORP
发明人： TAKEUCHI SUMIO , MUROOKA RIKICHI , SAKAMOTO ATSUSHI
IPC分类号： H03M1/10 , H03M1/06 , H03M1/08 , H03M1/12

5. 发明专利

JPS5750146A Signal selector 失效
标题翻译：信号选择器
公开(公告)号：JPS5750146A
公开(公告)日：1982-03-24
申请号：JP12504780
申请日：1980-09-09
申请人： Sony Tektronix Corp
发明人： SAKAMOTO ATSUSHI
IPC分类号： H04J3/04 , H03K5/00 , H04L5/22 , H04L5/24
CPC分类号： H04L5/245
摘要： PURPOSE:To prevent the production of error signal due to out of synchronism between a control signal and an input signal, by providing a latch circuit at an output of a multiplexer. CONSTITUTION:A multiplexer 6 selects input terminals 1-5 according to the 1st control signal of a control circuit 7. A latch circuit 8 is used to latch an output signal of the multiplexer 6, and latch operation is started by the 2nd control signal produced every time when the 1st control signal of the control circuit is switched. The 3rd control signal to release the latch operation is produced, when an output signal of the multiplexer 6 changes after a prescribed time from the latch operation start based on a signal obtained through giving delay the 2nd control signal with a delay circuit 9.
摘要翻译：目的：为了防止由于控制信号和输入信号之间的同步而产生误差信号，通过在多路复用器的输出端提供锁存电路。构成：复用器6根据控制电路7的第一控制信号选择输入端子1-5。锁存电路8用于锁存多路复用器6的输出信号，并通过产生的第二控制信号开始锁存操作每当控制电路的第一控制信号被切换时。当多路复用器6的输出信号基于通过延迟电路9给予延迟获得的第二控制信号而获得的信号时，从锁存操作开始经过规定时间后，产生解除锁存操作的第3控制信号。

6. 发明专利

JPH04143665A SIGNAL MEMORY METHOD 失效
公开(公告)号：JPH04143665A
公开(公告)日：1992-05-18
申请号：JP21079890
申请日：1990-08-08
申请人： SONY TEKTRONIX CORP
发明人： SAKAMOTO ATSUSHI
IPC分类号： G01R13/20 , G01D7/00 , G01D9/00 , G08C15/00
摘要： PURPOSE:To prevent an old data and a new data from being memorized together by disabling supply of a trigger signal or nullifying a second control signal until an address control signal specifies all addresses. CONSTITUTION:A CPU 9 outputs a first control signal to an address control circuit 8 and a RAM of selection memory circuit 3 writes a new data. When data is written for one cycle, the CPU 9 instructs the circuit 8 to trigger-enable AND gate for allowing a trigger signal of a trigger circuit 7 to be supplied to a delay counter. However, the RAM rewrites new data continuously and repeats it until the trigger signal is generated. After trigger enable, the delay counter which receives trigger signal counts clock pulses, outputs delay trigger signal which is a second control signal, and then stops writing operation or the AND gate is provided at a later stage of the delay counter, the second control signal is nullified until the circuit 8 specifies all addresses, and writing operation is stopped when the signal is valid.

7. 发明专利

JPH0145678B2 失效
公开(公告)号：JPH0145678B2
公开(公告)日：1989-10-04
申请号：JP12688480
申请日：1980-09-12
申请人： SONY TEKTRONIX CORP
发明人： SAKAMOTO ATSUSHI
IPC分类号： G01R13/20 , G01D7/02 , G08C15/06 , G08C19/00 , G11C27/00

8. 发明专利

JPS6351718A SIGNAL SELECTION DEVICE 失效
公开(公告)号：JPS6351718A
公开(公告)日：1988-03-04
申请号：JP17204387
申请日：1987-07-09
申请人： SONY TEKTRONIX CORP
发明人： SAKAMOTO ATSUSHI
IPC分类号： H03K17/00 , H04J3/04
摘要： PURPOSE:To prevent a crosstalk in a selection means from being generated, by making an input digital signal pass only by a gate means selected by the selection means corresponding to a digital control signal. CONSTITUTION:Input terminals 1-5 on which different input digital signals are impressed, are connected to the input terminals of a multiplexer 6 that is the selection means respectively, through wired OR gates 21-25 that are the gate means. The multiplexer 6 selects a desired input digital signal corresponding to a control signal from a control circuit 7. and supplies it to an output terminal 10. Meanwhile, a decoder 20 decodes the control signal from the control circuit 7, and controls the OR gates 21-25. In this way, since the gate means corresponding to the input digital signal not selected makes the selection means prevent the passage of the input digital signal, and supplies a constant logic level, a selected input digital signal is prevented from being affected by the crosstalk in the selection means.

9. 发明专利

JPH04143666A SIGNAL DISPLAY DEVICE 失效
公开(公告)号：JPH04143666A
公开(公告)日：1992-05-18
申请号：JP21079990
申请日：1990-08-08
申请人： SONY TEKTRONIX CORP
发明人： SAKAMOTO ATSUSHI
IPC分类号： G01R13/20 , G01D7/00 , G01R13/28 , G09G5/36
摘要： PURPOSE:To enable each input signal at different times to be compared easily by shifting a display position in a direction of time base of an input signal waveform of a plurality of channels to be memorized independently and freely for each channel. CONSTITUTION:When an AND gate 24 is forbidden, a trigger signal is fed to a delay counter 25 for setting clock pulses to be counted to a set value and for feeding a delay trigger signal to a control circuit 26, a selection memory circuit 3 becomes a READ mode and a multiplexer 21 selects an ADDER circuit. Then, a clock signal is counted 17, an address signal is fed to a circuit 20, a carrier signal is fed to a multiplexer 19 for enabling bias latch circuits 15 and 16 to be selected alternately for each generation of signal and a 2-channel signal memorized in the circuit 3 to be read out alternately for display. In this case, circuits 15 and 16 read out what is obtained by adding one to a memorized final address when writing is stopped for setting a start address. Therefore, by changing the memorized data, both or one signal waveform can be shifted in horizontal (time base) direction freely for easy comparison.

10. 发明专利

JPS6329789A IMAGE DISPLAY DEVICE 失效
公开(公告)号：JPS6329789A
公开(公告)日：1988-02-08
申请号：JP17309286
申请日：1986-07-23
申请人： SONY TEKTRONIX CORP
发明人： SAKAMOTO ATSUSHI
IPC分类号： G09G5/00 , G09G1/02 , G09G1/16 , G09G5/36 , G09G5/39 , G09G5/395

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