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1. 发明专利

JPS57166657A MEMORY CIRCUIT 失效
公开(公告)号：JPS57166657A
公开(公告)日：1982-10-14
申请号：JP5033081
申请日：1981-04-03
申请人： SONY CORP
发明人： NISHIOKA HISAO , FUKUDA JIYOUJI , SASAKI TADAO , MATSUMOTO YOSHIHIKO , OOKUBO YUTAKA , TAKEZAWA AKIRA
IPC分类号： G06F9/32 , G06F12/06 , G06F15/78
摘要： PURPOSE:To expand the spaces of addresses by accessing the operation code and operand of a data transfer instruction from a CPU to a memory from an instruction bank and also accessing the data to be executed from a data bank. CONSTITUTION:Random access memories (RAMs) 2 and 3 and a CPU1 are connected to each other through a data bus 4 and an address bus 5, the RAM2 and the RAM3 are used as an instruction bank and a data bank, respectively. The RAMs 2 and 3 are assigned to the spaces of the CPU1 and an instruction detecting circuit 11 supplies an instruction code fetching signal SS from the RAM2 to the RAM3. Thus, the operation code and the operand from the CPU1 are accessed from the RAM2, and data to be exectured by a memory transfer instruction is accessed from the RAM3. Consequently, the RAMs 2 and 3 use the address spaces in common, expanding the address spaces.

2. 发明专利

JPH10187628A INFORMATION PROCESSING METHOD 失效
公开(公告)号：JPH10187628A
公开(公告)日：1998-07-21
申请号：JP32805397
申请日：1997-11-28
申请人： SONY CORP
发明人： TAKEZAWA AKIRA
IPC分类号： G06F15/02
摘要： PROBLEM TO BE SOLVED: To easily record business card data of other persons and to easily record business card data on an individual in an other-person's information processor. SOLUTION: Business card data of an individual which are inputted corresponding to a business card column of the individual are stored in an individual' s business card storage part 10. The individual's business card data stored in the individual's business card storage part 10 are sent from a transmission part 14 to the other-person's information processor and other-person's business card data sent from the other-person's information processor are received by a reception part 16 and stored in an other-person's business card storage part 12.

3. 发明专利

JPH10143475A INFORMATION PROCESSOR 失效
公开(公告)号：JPH10143475A
公开(公告)日：1998-05-29
申请号：JP32750197
申请日：1997-11-28
申请人： SONY CORP
发明人： TAKEZAWA AKIRA
IPC分类号： G06F15/02
摘要： PROBLEM TO BE SOLVED: To prevent the recording of business card data from spending much time by transmitting his/her own business card data to another electronic notebook and receiving and storing the business card data of another person transmitted from the other electronic notebook when the start of a business card data exchange processing is commanded. SOLUTION: In the case that a user exchanges the business card, a business card exchange icon 8 displayed at a display 6 is indicated with a pen 4 and a business card exchange control part 18N is activated. At the time, the business card exchange control part 18N of the electronic notebook of an opposite party to exchange the business card is activated as well. The activated business card exchange control part 18N transmits business card exchange start signals to the electronic notebook of the opposite party through a transmission part 14. At the time of receiving response signals from the electronic notebook of the opposite party through a reception part 16, the business card exchange control part 18N transmits its own business card data to the electronic notebook of the opposite party through the transmission part 14, receives the business card data of the opposite party sent from the electronic notebook of the opposite party through the reception part 16 and records them in an another person business card storage part 12.

4. 发明专利

JPH03260718A INFORMATION INPUT CONTROLLER 失效
公开(公告)号：JPH03260718A
公开(公告)日：1991-11-20
申请号：JP5912690
申请日：1990-03-09
申请人： SONY CORP
发明人： HIRAYAMA TOMOHITO , TAKEZAWA AKIRA
IPC分类号： G06F15/02 , G06F3/033 , G06F3/041 , G06F3/048 , G06F17/40
摘要： PURPOSE:To easily and quickly change display contents and to design the information input controller compactly by changing the display contents at different speeds in accordance with the contact positions between an input pen and an input tablet. CONSTITUTION:A clock operating area 500 is provided with the display contents change instruction areas 300 and 310 where the numeric characters 200 and 210 are increased or decreased for 'hour' and 'minute', respectively. When an input pen is put down to the divided areas 300Da 300Dd and 310Da 310Dd of the areas 300 and 310 respectively, the reducing (changing) speed is successively slowed down for both characters 200 and 210. Meanwhile the increasing (changing) speed is gradually reduced for the characters 200 and 210 when the input pen is put down to the areas 300Ud 300Ua and 310Ud 310Ua respectively. Thus it is possible to easily and quickly change the display contents and also to design the information input controller compactly.

5. 发明专利

JPS58195265A Microcomputer 失效
标题翻译： MICROCOMPUTER
公开(公告)号：JPS58195265A
公开(公告)日：1983-11-14
申请号：JP7801782
申请日：1982-05-10
申请人： Sony Corp
发明人： FUKUDA JIYOUJI , TAKEZAWA AKIRA , OOKUBO YUTAKA , KOBAYASHI KENICHI , NAKAMURA TOSHINORI
IPC分类号： G06F15/16 , G06F13/40 , G06F15/17 , G06F15/177
CPC分类号： G06F15/17 , G06F13/4018
摘要： PURPOSE: To process two CPUs completely independently and simultaneously and to speed up the transmission/reception of data by arranging required peripheral circuits between the two independent CPUs.
CONSTITUTION: A transceiver 51 and a decoder 55 are connected between data buses 21W41 arranged between the CPUs 11, 31. An I/O address signal and a direction signal are inputted to the transceiver 51. In addition, latches 52, 53 are connected to the data bus 21 and an address bus 42. A driver 54 is connected to the address buses 22, 42 and a decoder 56 decodes the I/O address by a signal from the bus 22 and a control bus 23 and inputs the decoded signal to the latches 52, 53. Consequently, the CPUs 11, 31 can process programs completely independently and simultaneously in accordance with respective ROMs 12, 32 in the CPUs 11, 31 and also are available to access data at a high speed.
COPYRIGHT: (C)1983,JPO&Japio
摘要翻译：目的：完全独立和同时处理两个CPU，并通过在两个独立CPU之间安排所需的外围电路，加速数据的发送/接收。构成：收发器51和解码器55连接在布置在CPU11,31之间的数据总线21-41之间.I / O地址信号和方向信号被输入到收发器51.此外，锁存器52,53 连接到数据总线21和地址总线42.驱动器54连接到地址总线22,42，解码器56通过来自总线22和控制总线23的信号对I / O地址进行解码，并输入解码的信号到锁存器52,53。因此，CPU11,31可以根据CPU11,31中的相应ROM 12,32完全独立地并且同时处理程序，并且还可以以高速访问数据。

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