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1. 发明专利

JP2004336706A Receiving apparatus and semiconductor integrated circuit for radio signal processing 有权
标题翻译：接收装置和无线电信号处理的半导体集成电路
公开(公告)号：JP2004336706A
公开(公告)日：2004-11-25
申请号：JP2003402559
申请日：2003-12-02
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MURAKAMI MOTOKI , IGARASHI YUTAKA , YAMAMOTO AKIO , IKUTA ISAO , HARASAWA YOSHIAKI
IPC分类号： H04B1/30 , H04B1/04
摘要： PROBLEM TO BE SOLVED: To provide a receiving apparatus, transmitting apparatus and semiconductor integrated circuit for radio signal processing with the same incorporated therein in which offset between differential signals and between orthogonal signals is decreased and production yield can be improved. SOLUTION: In the receiving apparatus provided with a local oscillation circuit 8 for generating an oscillation signal of a desired frequency, a 90° phase shifter circuit 7 for generating a signal resulting from shifting a phase of the oscillation signal outputted from the local oscillation circuit at 90°, a first mixer 4Q for mixing one of differential received signals and the output signal of the 90° phase shifter circuit to output a differential signal of a converted frequency, and a second mixer 4I for mixing the other differential received signal and the output signal of the local oscillation circuit to output a differential signal of a converted frequency, a common-mode signal component average circuit 20 is provided for reducing the DC offset caused by a difference of common-mode signal components contained in the output signals of the first mixer and the second mixer. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种接收装置，发送装置和用于无线电信号处理的半导体集成电路，其中结合有差分信号之间的偏移和正交信号之间的偏移，并且可以提高生产率。解决方案：在设置有用于产生期望频率的振荡信号的本地振荡电路8的接收装置中，产生由本地输出的振荡信号的相位偏移产生的信号的90°移相器电路7 振荡电路为90°，用于混合差分接收信号之一的第一混频器4Q和90°移相器电路的输出信号以输出转换频率的差分信号;以及第二混频器4I，用于混合其它差分接收信号和本地振荡电路的输出信号以输出转换频率的差分信号，共模信号分量平均电路20用于减少由输出信号中包含的共模信号分量的差引起的DC偏移的第一混合器和第二混合器。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2004180281A Orthogonal mixer circuit and mobile terminal using the same 审中-公开
公开(公告)号：JP2004180281A
公开(公告)日：2004-06-24
申请号：JP2003361469
申请日：2003-10-22
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： IGARASHI YUTAKA , IKUTA ISAO , YAMAMOTO AKIO
IPC分类号： H03D7/14 , H03D7/16
CPC分类号： H03D7/165 , H03D2200/0019
摘要： PROBLEM TO BE SOLVED: To provide an orthogonal mixer circuit which can enlarge the amplitude of a local signal to improve the gain and noise characteristics, and to reduce the current consumption.
SOLUTION: The voltages of the current output terminals 202, 203 of a current branch circuit 200 are different, such that the voltages of current input terminals 25, 26 of current switch circuits 18, 19 are not mutually affected even of the amplitude of the local signal is large. Therefore, the amplitude of the local signal may be enlarged to improve the performance of an orthogonal mixer. Further, the bias currents of the current switch circuits 18, 19 and a V/I converting circuit 14 are commonly supplied via the current branch circuit by a DC current source 12, thereby reducing current consumption.
COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2009094734A Cut-off frequency automatic adjusting circuit and personal digital assistant 审中-公开
标题翻译：切断频率自动调节电路和个人数字助理
公开(公告)号：JP2009094734A
公开(公告)日：2009-04-30
申请号：JP2007262637
申请日：2007-10-05
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： IGARASHI YUTAKA , YAMAMOTO AKIO , KATSUBE YUSAKU
IPC分类号： H03H11/04
摘要： PROBLEM TO BE SOLVED: To automatically adjust a filter cut-off frequency with a large capacitance ratio, and to shorten the time required for automatic adjustment.
SOLUTION: A register for correcting error and a filter cut-off frequency automatic adjusting circuit are provided for each feedback capacitance and non-feedback capacitance (ground capacitance) of a channel filter circuit. Thus, the filter cut-off frequency can be adjusted without enlarging the error caused by a capacitance difference between the feedback capacitance and non-feedback capacitance.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：以大电容比自动调节滤波器截止频率，缩短自动调整所需的时间。解决方案：为通道滤波电路的每个反馈电容和非反馈电容（接地电容）提供一个用于校正误差的寄存器和一个滤波器截止频率自动调节电路。因此，可以调节滤波器截止频率而不会增大由反馈电容和非反馈电容之间的电容差引起的误差。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008271202A Low noise amplifier circuit with gain switching 有权
标题翻译：低噪声放大器电路与增益切换
公开(公告)号：JP2008271202A
公开(公告)日：2008-11-06
申请号：JP2007111537
申请日：2007-04-20
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： IGARASHI YUTAKA , YAMAMOTO AKIO
IPC分类号： H03F1/26 , H03G3/10
CPC分类号： H03G1/0088 , H03F1/22 , H03F3/19 , H03F3/72 , H03F2200/294 , H03F2200/366 , H03F2200/492 , H03F2203/7206
摘要： PROBLEM TO BE SOLVED: To provide a LNA (low noise amplifier) with gain switching capable of suppressing a deterioration in a noise figure.
SOLUTION: The LNA with gain switching having a first transistor group (Q11 to Q18) and a second transistor group (Q21 to Q28) has a resistor R4 connected between the emitter of the transistor Q21 and the collector of a transistor Q1, and a resistor R5 connected to the emitters of the transistors Q22 to Q28 and the collector of the transistor Q1, having a resistor R5 composed of a resistance value being as 1/7 times as high as that of the resistor R4, and has no deterioration in a noise figure because isolation of the transistors Q21 to Q28, and the transistors Q1 and Q11 to Q18 which are turned off by the resistor R4 and the resistor R5 in a high gain mode is secured.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有能够抑制噪声系数恶化的增益切换的LNA（低噪声放大器）。解决方案：具有第一晶体管组（Q11至Q18）和第二晶体管组（Q21至Q28）的具有增益切换的LNA具有连接在晶体管Q21的发射极和晶体管Q1的集电极之间的电阻器R4，连接到晶体管Q22〜Q28的发光极和晶体管Q1的集电极的电阻器R5，其电阻器R5为电阻值为电阻器R4的电阻值的1/7倍，不劣化因为确保了以高增益模式被电阻器R4和电阻器R5截止的晶体管Q21至Q28以及晶体管Q1和Q11至Q18的隔离。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008177645A Pll control system 审中-公开
标题翻译： PLL控制系统
公开(公告)号：JP2008177645A
公开(公告)日：2008-07-31
申请号：JP2007006748
申请日：2007-01-16
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： IKUTA ISAO , IGARASHI YUTAKA , SUGIYAMA YOSHIICHI
IPC分类号： H03L7/10 , H03L7/087 , H03L7/093 , H03L7/187
摘要： PROBLEM TO BE SOLVED: To provide a PLL control system capable of suppressing variance in loop band even when charge pump currents are set for each band of a VCO. SOLUTION: The PLL control system includes: a TCX0 8; a frequency divider B8; the VCO 4 having a plurality of bands; a frequency divider A5; a phase comparator 6 which compares two frequency-division signals of the frequency dividers A5 and B8 with each other; a loop filter 2 which outputs a voltage to the VCO 4; a charge pump circuit 3 which supplies a current to the loop filter 2 according to the comparison signal of the phase comparator 6; a precharging circuit 1 which precharges the loop filter 2; and a control section 9, the control section 9 discretely controlling the precharging by the precharging circuit 1 based upon discrete information preset in accordance with the plurality of bands. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：即使为VCO的每个频带设置电荷泵电流，提供能够抑制环路频带变化的PLL控制系统。解决方案：PLL控制系统包括：TCX0 8; 分频器B8; VCO4具有多个频带; 分频器A5; 相位比较器6，其将分频器A5和B8的两个分频信号彼此进行比较; 环路滤波器2，其向VCO4输出电压; 电荷泵电路3，其根据相位比较器6的比较信号向环路滤波器2提供电流; 对环路滤波器2进行预充电的预充电电路1; 以及控制部分9，控制部分9基于根据多个频带预设的离散信息离散地控制预充电电路1的预充电。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2006054547A Optimizing method of receiving apparatus and receiving characteristic 审中-公开
标题翻译：接收装置和接收特性的优化方法
公开(公告)号：JP2006054547A
公开(公告)日：2006-02-23
申请号：JP2004233165
申请日：2004-08-10
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YAMAMOTO AKIO , IGARASHI YUTAKA
IPC分类号： H04B1/10 , H04B1/30
摘要： PROBLEM TO BE SOLVED: To reduce a secondary distortion without using a filter, such as an RFSAW, etc., for converting a high frequency signal. SOLUTION: In a receiving apparatus which receives a digitally modulated signal, the circuit bias of a low noise amplifier 3, mixers 4, 5, the whole balancing is maintained by correcting the circuit part bias of a low noise amplifier 3, mixers 4, 5, a local buffer 10, etc., and secondary distortion jamming is suppressed. Since the secondary distortion jamming appears as the deterioration of an S/N ratio in a demodulator, this S/N ratio is detected, and a bias is corrected so that the S/N ratio may become the maximum. Consequently, the secondary distortion jamming is suppressed. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了减少二次失真，而不使用诸如RFSAW等的滤波器来转换高频信号。解决方案：在接收数字调制信号的接收装置中，低噪声放大器3，混频器4,5的电路偏置，通过校正低噪声放大器3的电路部分偏置来保持整体平衡，混频器 4,5，本地缓冲器10等，并且二次失真干扰被抑制。由于二次失真干扰出现在解调器中的S / N比的劣化，因此检测到该S / N比，并且校正偏差使得S / N比可能变得最大。因此，二次失真干扰被抑制。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2008060882A Amplifier circuit 审中-公开
标题翻译：放大器电路
公开(公告)号：JP2008060882A
公开(公告)日：2008-03-13
申请号：JP2006234915
申请日：2006-08-31
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KATSUBE YUSAKU , YAMAMOTO AKIO , IKUTA ISAO , IGARASHI YUTAKA
IPC分类号： H03F3/16 , H03G3/10 , H04B1/30
摘要： PROBLEM TO BE SOLVED: To provide a small amplifier circuit of low current consumption by which DC offset in gain switching by an AGC is reduced in a direct conversion circuit.
SOLUTION: In the amplifier circuit equipped with an amplifier, capacitance C10 and capacitance C20 for DC cut are connected to preceding stages of input circuits MA10, MA20 of the amplifier, switches MN10, MP10, MN20, MP20 for bias are connected between input circuits MA10, MA20 of the amplifier and a reference bias point and the input circuits MA10, MA20 of the amplifier are constituted by MOSFETs. Small scale and lower current consumption are made possible by constituting the amplifier circuit so as to turn on the switches for bias immediately before an amplifying operation, to give the bias to the input circuits of the amplifier and to turn the switches off at the amplifying operation.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种低电流消耗的小放大器电路，通过其在直接转换电路中减小AGC增益切换中的DC偏移。
解决方案：在配备放大器的放大器电路中，用于直流切断的电容C10和电容C20连接到放大器的输入电路MA10，MA20的前级，用于偏置的开关MN10，MP10，MN20，MP20连接在放大器的输入电路MA10，MA20和参考偏置点以及放大器的输入电路MA10，MA20由MOSFET构成。通过构成放大电路，可以实现小型化和低电流消耗，以便在放大操作之前接通用于偏置的开关，从而给放大器的输入电路提供偏置，并在放大操作时关断开关。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007215140A Semiconductor integrated circuit and semiconductor integrated circuit for radio communication 有权
标题翻译：半导体集成电路和半导体集成电路无线电通信
公开(公告)号：JP2007215140A
公开(公告)日：2007-08-23
申请号：JP2006035671
申请日：2006-02-13
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： IGARASHI YUTAKA , KATSUBE YUSAKU , YAMAMOTO AKIO
IPC分类号： H04L25/02 , H04B1/30
CPC分类号： H04B1/30
摘要： PROBLEM TO BE SOLVED: To provide a technology of a semiconductor integrated circuit which can secure a desired reception characteristic even if a circuit block requiring a clock signal and a circuit block requiring a low noise reception characteristic are arranged within the same chip.
SOLUTION: In a reception circuit of a direct conversion mode which applies a semiconductor integrated circuit for radio communication having a PLL 130 requiring a clock signal and an LNA 20 requiring a low noise reception characteristic, a variable connection line 180 is provided between clock signal buffers 110 and 120 of an input stage of the PLL 130, and bonding of the variable connection line 180 in a high-harmonic frequency of the clock signal and an input terminal of an LNA 20, and bonding of the variable connection line 180 and a GND terminal are equalized. If the input terminal and the GND terminal of the LNA 20 are excited in phase, nothing is outputted from the LNA 20. Therefore, no clock signal higher harmonic wave exists in the output of the LNA 20.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：即使需要时钟信号的电路块和需要低噪声接收特性的电路块布置在同一芯片内，也可以提供能够确保期望的接收特性的半导体集成电路的技术。解决方案：在应用用于具有需要时钟信号的PLL 130的无线电通信的半导体集成电路和需要低噪声接收特性的LNA 20的直接转换模式的接收电路中，可变连接线180设置在 PLL 130的输入级的时钟信号缓冲器110和120以及时钟信号的高谐波频率和LNA 20的输入端的可变连接线180的接合，以及可变连接线180 并且GND端子相等。如果LNA 20的输入端子和GND端子被同相激励，则从LNA20不会输出任何内容。因此，LNA 20的输出中不存在时钟信号高次谐波。（C） 2007年，日本特许厅和INPIT

9. 发明专利

JP2005039765A Multimode radio terminal and radio transmitting/receiving part 审中-公开
标题翻译：多模无线终端和无线传输/接收部分
公开(公告)号：JP2005039765A
公开(公告)日：2005-02-10
申请号：JP2003429484
申请日：2003-12-25
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SUGIYAMA YOSHIICHI , NODA MASAKI , KATAGISHI MAKOTO , IGARASHI YUTAKA
IPC分类号： H04B1/10 , H04B1/3822 , H04B1/40 , H04B17/18 , H04B17/29 , H04B17/382 , H04J3/00 , H04W24/08 , H04W36/36 , H04W76/02 , H04W88/02 , H04W88/10 , H04Q7/38 , H04J13/00 , H04Q7/22
CPC分类号： H04B1/406 , H04B1/109
摘要： PROBLEM TO BE SOLVED: To provide a multimode radio terminal suitable for monitoring the reception level of a base station that is an inter-system handover destination. SOLUTION: The multimode radio terminal comprises a first radio transmitting/receiving part for GSM, a second radio transmitting/receiving part for WCDMA, a communication processing part and an antenna switch part which are connected to these radio transmitting/receiving parts, and monitors the level of a received signal from a GSM base station via the first radio transmitting/receiving part during the communications with a WCDMA network via the second radio transmitting/receiving part. The communication processing part decides whether or not level monitoring is interfered by a WCDMA transmission signal from the relationship between a transmission frequency of WCDMA and the reception frequency of the GSM base station and when the interference occurs, circuit properties of any one of the first and the second radio transmitting/receiving parts are changed to suppress the interference. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供适合于监视作为系统间切换目的地的基站的接收电平的多模式无线终端。解决方案：多模无线终端包括用于GSM的第一无线电发射/接收部分，用于WCDMA的第二无线电发射/接收部分，通信处理部分和天线切换部分，其连接到这些无线电发射/接收部分，并且在经由第二无线电发送/接收部分与WCDMA网络通信期间经由第一无线电发送/接收部分监视来自GSM基站的接收信号的电平。通信处理部根据WCDMA的发送频率与GSM基站的接收频率之间的关系来判定电平监视是否受到WCDMA发送信号的干扰，当发生干扰时，第一和第改变第二无线电发送/接收部分以抑制干扰。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2010141651A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2010141651A
公开(公告)日：2010-06-24
申请号：JP2008316620
申请日：2008-12-12
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： IGARASHI YUTAKA , YAMAMOTO AKIO , KATSUBE YUSAKU
IPC分类号： H03H11/04
摘要： PROBLEM TO BE SOLVED: To reduce an undesirable change of a frequency characteristic of a built-in filter depending on the change of a power supply voltage. SOLUTION: This semiconductor integrated circuit includes a calibration circuit 200, and a built-in capacitor 70:151 has capacitors and switches. V-I converters 30, 20 convert a reference voltage into current, and time integrators 40, 50 responding to current execute time integration of the capacitor 70, and a voltage comparator 80 compares the reference voltage with terminal voltage of the built-in capacitor 70. Time integration and voltage comparison are executed during a calibration operation, and the results of thereof are stored in a latch 90. A frequency characteristic of a built-in filter 150 is determined according to a storage result of the latch 90 when the calibration operation is completed. A stabilization voltage V REF is supplied to a gate of an N-channel MOS transistor of a switch SWO of the V-I converters 30, 20 during the calibration operation. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：根据电源电压的变化来减少内置滤波器的频率特性的不希望的变化。解决方案：该半导体集成电路包括校准电路200，并且内置电容器70：151具有电容器和开关。 VI转换器30,20将参考电压转换为电流，并且响应于电容器70的当前执行时间积分的时间积分器40,50和电压比较器80将参考电压与内置电容器70的端子电压进行比较。时间在校准操作期间执行积分和电压比较，并且其结果被存储在锁存器90中。当校准操作完成时，根据锁存器90的存储结果确定内置滤波器150的频率特性。在校准操作期间，向V-I转换器30,20的开关SWO的N沟道MOS晶体管的栅极提供稳定电压V SB。版权所有（C）2010，JPO＆INPIT

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