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1. 发明专利

JP2012252216A Data driver for panel display device 有权
标题翻译：面板显示设备的数据驱动器
公开(公告)号：JP2012252216A
公开(公告)日：2012-12-20
申请号：JP2011125519
申请日：2011-06-03
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： TSUCHI HIROSHI
IPC分类号： G09G3/36 , G02F1/133 , G09G3/20 , G09G3/30 , H01L51/50
CPC分类号： G09G3/006 , G09G3/2011 , G09G3/3291 , G09G3/3688 , G09G2300/043 , G09G2310/027 , G09G2310/0291 , G09G2330/12
摘要： PROBLEM TO BE SOLVED: To provide a data driver for a panel display device that enables a uniformity inspection of dynamic characteristics between outputs and the like to be carried out even in a structure where correction resistors for correcting resistance differences between lead wires are provided in the data driver.SOLUTION: A data driver for a panel display device comprises: a plurality of driver output terminals connecting to a plurality of data lines of a display panel, and a plurality of output circuits each outputting output signals from the plurality of driver output terminals. Each of the plurality of output circuits comprises: an output buffer that outputs the output signal; a first resistor one end of which connects to one driver output terminal; a first switch and a second resistor connecting between the output node of the output buffer and the other end of the first resistor in series; and a second switch connecting between the output node of the output buffer and the other end of the first resistor in parallel with the first switch and the second resistor.
摘要翻译：要解决的问题：为了提供一种用于面板显示装置的数据驱动器，其能够对要执行的输出之类的动态特性进行均匀性检查，即使在用于校正引线之间的电阻差的校正电阻器在数据驱动程序中提供。解决方案：面板显示装置的数据驱动器包括：连接到显示面板的多个数据线的多个驱动器输出端子，以及多个输出电路，每个输出电路从多个驱动器输出端子输出输出信号。所述多个输出电路中的每一个包括：输出所述输出信号的输出缓冲器; 第一电阻器的一端连接到一个驱动器输出端子; 连接在所述输出缓冲器的输出节点和所述第一电阻器的另一端串联的第一开关和第二电阻器; 以及第二开关，其连接在所述输出缓冲器的输出节点与所述第一电阻器的另一端并联于所述第一开关和所述第二电阻器。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2011205482A Digital/analog converter circuit, data driver, and display device 有权
标题翻译：数字/模拟转换器电路，数据驱动器和显示设备
公开(公告)号：JP2011205482A
公开(公告)日：2011-10-13
申请号：JP2010071921
申请日：2010-03-26
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： TSUCHI HIROSHI
IPC分类号： H03M1/68 , H03M1/76
CPC分类号： G09G3/3688 , G09G3/3696 , G09G2310/027 , G09G2330/028
摘要： PROBLEM TO BE SOLVED: To provide a digital/analog converter circuit, data driver and display device, wherein DNL deterioration can be prevented by allowing the area to be reduced by reducing the number of reference voltages.SOLUTION: Reference voltages of a reference voltage aggregate are divided into reference voltage groups 20-1 to 20-(zS+1). A decoder 10 is provided correspondingly to each of the reference voltage groups and includes: sub decoders 11-1 to 11-(zS+1) for selecting a reference voltage which is assigned to a column corresponding to a value of a first bit group of an input digital signal, respectively, from the reference voltages of the reference voltage group; and a sub decoder 13 which inputs outputs of the sub decoders and selects first and second voltages, from among the reference voltages selected by the sub decoders, in accordance with a value of a second bit group of the input digital signal. A interpolation circuit 30 inputs the first and second voltages selected by the decoder and outputs voltage level wherein two voltages are interpolated at interpolation ratio of one to one.
摘要翻译：要解决的问题：提供数字/模拟转换器电路，数据驱动器和显示装置，其中可以通过减少参考电压的数量来减小面积来防止DNL劣化。解决方案：参考电压聚集体的参考电压分为参考电压组20-1至20-（zS + 1）。解码器10对应于每个参考电压组提供，并且包括：子解码器11-1至11-（zS + 1），用于选择分配给与第一位组的值对应的列的参考电压分别来自参考电压组的参考电压的输入数字信号; 以及子解码器13，其输入子解码器的输出，并根据输入数字信号的第二位组的值从子解码器选择的参考电压中选择第一和第二电压。内插电路30输入由解码器选择的第一和第二电压并输出电压电平，其中两个电压以插值比为1比1进行内插。

3. 发明专利

JP2012124701A Level shift circuit and drive circuit having the same 有权
标题翻译：水平移位电路和驱动电路
公开(公告)号：JP2012124701A
公开(公告)日：2012-06-28
申请号：JP2010273562
申请日：2010-12-08
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： TSUCHI HIROSHI
IPC分类号： H03K19/0185 , G02F1/133 , G09G3/20 , G09G3/30 , G09G3/36 , H01L51/50
CPC分类号： G09G3/3696 , G09G3/3258 , G09G5/00 , G09G2310/027 , G09G2310/0289 , H03K3/356165 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To provide a level shift circuit that can easily convert a low amplitude signal into a high amplitude signal.SOLUTION: The level shift circuit includes: NMOS transistors M1, M2 connected between a power terminal E1 and output nodes 3, 4, respectively, and receiving low amplitude input signals at control terminals, respectively; PMOS transistors M3, M4 connected between a power terminal E2 and the output nodes 3, 4, respectively; a PMOS transistor M5 connected between a gate of the PMOS transistor M3 and the output node 4 and connected at a gate to the output node 3; a PMOS transistor M6 connected between a gate of the PMOS transistor M4 and the output node 3 and connected at a gate to the output node 4; a load element 11 operative to change a gate voltage in a direction to turn off the PMOS transistor M3; and a load element 12 operative to change a gate voltage in a direction to turn off the PMOS transistor M4.
摘要翻译：要解决的问题：提供能够容易地将低振幅信号转换成高振幅信号的电平移位电路。电平移位电路包括：分别连接在电源端子E1和输出节点3,4之间的NMOS晶体管M1，M2，并分别在控制端子处接收低幅度输入信号; 分别连接在电源端子E2和输出节点3,4之间的PMOS晶体管M3，M4; 连接在PMOS晶体管M3的栅极和输出节点4之间并连接到输出节点3的栅极的PMOS晶体管M5; 连接在PMOS晶体管M4的栅极和输出节点3之间并连接到输出节点4的栅极的PMOS晶体管M6; 负载元件11，用于在关闭PMOS晶体管M3的方向上改变栅极电压; 以及负载元件12，其操作以在关断PMOS晶体管M4的方向上改变栅极电压。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2011172100A Decoder and data driver of display device using the same 有权
标题翻译：使用该显示装置的解码器和数据驱动器
公开(公告)号：JP2011172100A
公开(公告)日：2011-09-01
申请号：JP2010035109
申请日：2010-02-19
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： TSUCHI HIROSHI , DOI NOBUYASU
IPC分类号： H03M1/76 , G02F1/133 , G09G3/20 , G09G3/30 , G09G3/36 , H03M1/70
CPC分类号： G09G3/3688 , G09G3/3283 , G09G3/3291 , G09G2310/027
摘要： PROBLEM TO BE SOLVED: To reduce an area by reducing the gate size of a switch transistor and to expand a range of voltage that can be output. SOLUTION: A decoder includes: a reference voltage generating circuit 20 that outputs first and second reference voltage groups 20A, 20B each respectively belonging to first and second voltage sections that do not overlap each other; and a sub-decoder 10 that receives the first and second reference voltage groups and selects a reference voltage corresponding to an input digital signal. The decoder includes a first sub-decoder 11 that receives the first reference voltage group 20A, a second sub-decoder 12 that receives the second reference voltage group 20B, and a third sub-decoder 13 that receives a reference voltage selected by the second sub-decoder 12 and outputs it to the first sub-decoder 11 or an output terminal 5. The sub-decoders 11, 12, 13 respectively include transistors MP1, MP2, MP3 wherein source voltages Vbp1, Vbp2 are supplied to a back gate. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过减小开关晶体管的栅极尺寸并扩大可输出的电压范围来减小面积。解码器包括：参考电压产生电路20，其输出分别属于彼此不重叠的第一和第二电压部分的第一和第二参考电压组20A，20B; 以及子解码器10，其接收第一和第二参考电压组并选择与输入数字信号相对应的参考电压。解码器包括接收第一参考电压组20A的第一子解码器11，接收第二参考电压组20B的第二子解码器12和接收第二子编码器选择的参考电压的第三子解码器13 - 解码器12并将其输出到第一子解码器11或输出端子5.子解码器11,12,13分别包括晶体管MP1，MP2，MP3，其中源电压Vbp1，Vbp2被提供给后门。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2011049779A Level shift circuit, and driver and display device using the same 有权
标题翻译：水平移位电路，以及使用该电平的驱动器和显示装置
公开(公告)号：JP2011049779A
公开(公告)日：2011-03-10
申请号：JP2009195930
申请日：2009-08-26
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： TSUCHI HIROSHI
IPC分类号： H03K19/0185 , G09G3/20
CPC分类号： G09G3/20 , G09G2310/027 , G09G2310/0289 , H03K19/018521
摘要： PROBLEM TO BE SOLVED: To provide a high-speed level shift circuit that prevents an increase in circuit scale. SOLUTION: The level shift circuit includes third circuits M3, M1 and M2 which are connected between a first power supply terminal E1 for supplying first voltage VE1 and a second power supply terminal E2 for supplying second voltage VE2, and makes the first circuit M4 conductive when the input signal IN of the level shift circuit shows a value corresponding to third voltage VE3, and makes the first circuit M4 non-conductive regardless of the value of the input signal IN when an output terminal 4 shows a value corresponding to the first voltage VE1. A second circuit M5 is made conductive when the inverted signal INB of the input signal shows a value corresponding to the third voltage VE3, and is made non-conductive when the inverted signal INB of the input signal shows a value corresponding to fourth voltage VE4, wherein the relation of the first to fourth voltage is VE2≤VE4 COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种防止电路规模增加的高速电平移位电路。解决方案：电平移位电路包括连接在用于提供第一电压VE1的第一电源端子E1和用于提供第二电压VE2的第二电源端子E2之间的第三电路M3，M1和M2，并使第一电路当电平移位电路的输入信号IN显示对应于第三电压VE3的值时，M4导通，并且当输出端子4显示对应于第二电压VE3的值时，不管输入信号IN的值如何，使第一电路M4不导通第一电压VE1。当输入信号的反相信号INB表示对应于第三电压VE3的值时，第二电路M5导通，并且当输入信号的反相信号INB表示对应于第四电压VE4的值时，使第二电路M5导通，其中第一至第四电压的关系为VE2≤VE4

6. 发明专利

JP2013042501A Level shift circuit, and driver and display device using the same 有权
标题翻译：水平移位电路，以及使用该电平的驱动器和显示装置
公开(公告)号：JP2013042501A
公开(公告)日：2013-02-28
申请号：JP2012179277
申请日：2012-08-13
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： TSUCHI HIROSHI
IPC分类号： H03K19/0185 , G09G3/20 , G09G3/30 , G09G3/36 , H03K17/00
摘要： PROBLEM TO BE SOLVED: To provide a level shift circuit that converts a low amplitude input signal to a high amplitude signal at high speed.SOLUTION: The level shift circuit includes: a first level shift circuit 10 for setting one of first and second output terminals to a first voltage level; a second level shift circuit 20 connected between a second voltage terminal and the first and second output terminals to set the other of the first and second output terminals to a second voltage level; and means for, in response to a first control signal, performing the control of disconnecting a current path between the second feed terminal and one of the output terminals which is brought to the second voltage level at the time when first and second input signals are input into first and second input terminals, for a predetermined period including the time when the first and second input signals are input into the first and second input terminals and, after the predetermined period, recovering the current path between the one output terminal and the second feed terminal from the disconnection. The first and second output terminals have a higher output amplitude than the first and second input signals.
摘要翻译：要解决的问题：提供一种将低振幅输入信号以高速转换成高振幅信号的电平移位电路。解决方案：电平移位电路包括：第一电平移位电路10，用于将第一和第二输出端中的一个设置为第一电压电平; 连接在第二电压端子与第一和第二输出端子之间的第二电平移位电路20将第一和第二输出端子中的另一个设置为第二电压电平; 以及用于响应于第一控制信号执行断开第二馈电端子与输入端子之间的电流路径的控制的装置，所述电流路径在输入第一和第二输入信号时被带到第二电压电平进入第一和第二输入端子一段预定的周期，包括第一和第二输入信号被输入到第一和第二输入端的时间，并且在预定时间段之后恢复在一个输出端和第二输入之间的电流路径终端从断开连接。第一和第二输出端子具有比第一和第二输入信号更高的输出幅度。版权所有（C）2013，JPO＆INPIT

7. 发明专利

JP2012114628A Output circuit, data driver and display device 有权
标题翻译：输出电路，数据驱动器和显示设备
公开(公告)号：JP2012114628A
公开(公告)日：2012-06-14
申请号：JP2010261082
申请日：2010-11-24
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： TSUCHI HIROSHI
IPC分类号： H03F3/45 , G02F1/133 , G02F1/1368 , G09G3/20 , G09G3/30 , G09G3/36 , H01L51/50 , H03K17/687
CPC分类号： G09G3/3677 , G09G3/3258 , G09G3/3291 , G09G3/3688 , G09G2300/0426 , G09G2310/0289 , G09G2310/0291 , G09G2330/021 , H03F1/0261 , H03F3/45179 , H03F3/4526 , H03F2200/18 , H03F2200/27 , H03F2203/45562 , H03F2203/45614 , H03F2203/45618 , H03F2203/45644 , H03F2203/45674 , H03F2203/45676 , H03F2203/45724 , H03F2203/45728
摘要： PROBLEM TO BE SOLVED: To provide an output circuit, a data driver and a display device that suppress a delay of an output signal at the time of output period switching.SOLUTION: The output circuit includes differential amplification circuits 110, 105, an output amplification circuit 120, a first control circuit 160, an input terminal 101, an output terminal 104, and first to third power terminals VDD, VSS, VML. The differential amplification circuit includes a differential input stage 110 for inputting an input signal to the input terminal and an output signal at the output terminal, and first and second current mirrors 130, 140. The output amplification circuit 120 includes a first transistor 121 of a first conductivity type connected between the first power terminal VDD and the output terminal 104, and a second transistor 122 of a second conductivity type connected between the output terminal 104 and the third power terminal VML. The first control circuit 160 includes a third transistor 161 of the first conductivity type, and a first switch 162.
摘要翻译：要解决的问题：提供一种在输出周期切换时抑制输出信号的延迟的输出电路，数据驱动器和显示装置。
解决方案：输出电路包括差分放大电路110,105，输出放大电路120，第一控制电路160，输入端101，输出端104和第一至第三电源端子VDD，VSS，VML。差分放大电路包括用于将输入信号输入到输入端的差分输入级110和输出端的输出信号以及第一和第二电流镜130,140。输出放大电路120包括：第一晶体管121，连接在第一电源端子VDD和输出端子104之间的第一导电类型以及连接在输出端子104和第三电力端子VML之间的第二导电类型的第二晶体管122。第一控制电路160包括第一导电类型的第三晶体管161和第一开关162。（C）2012，JPO和INPIT

8. 发明专利

JP2012034066A Digital/analog conversion circuit and display driver 有权
标题翻译：数字/模拟转换电路和显示驱动器
公开(公告)号：JP2012034066A
公开(公告)日：2012-02-16
申请号：JP2010169951
申请日：2010-07-29
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： TSUCHI HIROSHI
IPC分类号： H03M1/68 , G02F1/133 , G09G3/20 , G09G3/30 , G09G3/36 , H01L51/50
CPC分类号： G09G3/3696 , G09G3/3688 , G09G2310/027 , G09G2310/0289 , G09G2330/021 , H03M1/66
摘要： PROBLEM TO BE SOLVED: To provide a digital/analog converter, a data driver and a display device which suppress increase in the number of switches fabricated within a CMOS and gate width to deter an increase of area.SOLUTION: In a digital/analog converter, a reference voltage aggregate 80 includes first and second reference voltage groups 81 and 82. A decoder 100 includes first and second sub-decoder parts 10 and 20 to which higher-order (m-n)-bit signals in m-bit digital signals are input in common, and third and fourth sub-decoder parts 30 and 40 to which lower-order n-bit signals in the m-bit digital signals are input in common. The first and third sub-decoder parts 10 and 30 are composed of first conductive type transistors, and the second and fourth sub-decoder parts 20 and 40 are composed of second conductive type transistors. An amplifier circuit 50 averages voltages received at its input with a predetermined weighting and outputs the weighted averaged voltage as an analog signal corresponding to the m-bit digital signal, from an output terminal 51.
摘要翻译：要解决的问题：提供数字/模拟转换器，数据驱动器和显示装置，其抑制在CMOS和门宽度内制造的开关数量的增加以阻止面积的增加。解决方案：在数字/模拟转换器中，参考电压聚集体80包括第一和第二参考电压组81和82.解码器100包括第一和第二子解码器部分10和20，高阶（mn） m位数字信号中的位信号被公共输入，并且m位数字信号中的低位n位信号被共同输入的第三和第四子解码器部分30和40。第一和第三子解码器部件10和30由第一导电型晶体管组成，第二和第四子解码器部件20和40由第二导电型晶体管组成。放大器电路50以预定的加权平均在其输入处接收的电压，并从输出端子51输出加权平均电压作为与m位数字信号对应的模拟信号。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2012018388A Output circuit, data driver, and display device 有权
标题翻译：输出电路，数据驱动器和显示设备
公开(公告)号：JP2012018388A
公开(公告)日：2012-01-26
申请号：JP2011096240
申请日：2011-04-22
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： TSUCHI HIROSHI
IPC分类号： G09G3/30 , G09G3/20 , G09G3/36 , H03F1/02 , H03F3/45
CPC分类号： G09G3/3275 , G09G3/3688 , G09G2310/0286 , G09G2310/0289
摘要： PROBLEM TO BE SOLVED: To attain a symmetric property of output voltage waveforms in charging and discharging even in a configuration capable of responding to a high-speed operation, suppressing the power consumption and simplifying a differential stage into a single conductivity type.SOLUTION: This output circuit includes: a differential input stage which comprises first differential pair 111 and 112, a first current mirror 130, a second current mirror 140, a first floating current source circuit 150, and a second floating current source circuit 160; an output amplifier stage 110 which comprises a first transistor 101 of a first conductivity type and a second transistor 102 of a second conductivity type; and a current control circuit 120 which comprises first and second current sources 121 and 123, a third transistor 103, a fourth transistor 105, third and fourth current sources 122 and 124, a fifth transistor 104, and a sixth transistor 106.
摘要翻译：解决方案：即使在能够对高速运转进行响应的结构中，即使在充放电时也能获得输出电压波形的对称性，可以抑制功耗，简化差分级为单一导电型。解决方案：该输出电路包括：差分输入级，其包括第一差分对111和112，第一电流镜130，第二电流镜140，第一浮动电流源电路150和第二浮动电流源电路 160; 输出放大器级110，其包括第一导电类型的第一晶体管101和第二导电类型的第二晶体管102; 以及电流控制电路120，其包括第一和第二电流源121和123，第三晶体管103，第四晶体管105，第三和第四电流源122和124，第五晶体管104和第六晶体管106。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2011209556A Voltage level selection circuit and display driver 有权
标题翻译：电压水平选择电路和显示驱动器
公开(公告)号：JP2011209556A
公开(公告)日：2011-10-20
申请号：JP2010077992
申请日：2010-03-30
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： TSUCHI HIROSHI
IPC分类号： G09G3/30 , G02F1/133 , G09G3/20 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/3291 , G09G3/3614 , G09G2310/027
摘要： PROBLEM TO BE SOLVED: To provide a data driver including a decoder which suppresses the number of elements, the number of wire connection between Pch and Nch, and the area.SOLUTION: The decoder includes a first subdecoder (SD) that receives a first level voltage group, outputs a voltage selected according to lower L bits of N bit data; a second SD that receives a second-level voltage group, and outputs a voltage selected according to the lower L bits; a third SD that selects one of the voltages selected by the first and second subdecoders according to upper M bits; a fourth SD, that outputs the voltage selected from the third-level voltage group according to lower P bits; a fifth SD that selects one of the voltages output from the fourth subdecoder according to upper Q bits; and a sixth SD, that controls conduction or nonconduction between the output of the first SD and the output of the fourth SD based on K bits. The first, second and third SDs comprise switches of first polarity, and the fourth, fifth and sixth SD2 comprise switches of second polarity.
摘要翻译：要解决的问题：提供一种数据驱动器，其包括抑制元件数量，Pch和Nch之间的有线连接数量以及面积的解码器。解码器包括：第一子编码器（SD），其接收第一级输出根据N位数据的较低L位选择的电压; 第二SD，其接收二级电压组，并输出根据低L位选择的电压; 第三SD，其根据高M位选择由第一和第二子编码器选择的电压之一; 第四SD，根据低P位输出从第三电平电压组选择的电压; 第五SD，根据高Q位选择从第四子编码器输出的电压之一; 以及第六SD，其基于K位来控制第一SD的输出和第四SD的输出之间的导通或非导通。第一，第二和第三SD包括第一极性的开关，第四，第五和第六SD2包括第二极性的开关。

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