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1. 发明专利

JP2007110110A Method of forming trench transistor and pertinent trench transistor 审中-公开
标题翻译：形成晶体管和恒温晶体管的方法
公开(公告)号：JP2007110110A
公开(公告)日：2007-04-26
申请号：JP2006270791
申请日：2006-10-02
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： RICHARD LUYKEN , MOLL HANS-PETER , POPP MARTIN , SCHLOESSER TILL , MARC STRASSER , WEIS ROLF
IPC分类号： H01L29/78 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/26586 , H01L29/66537 , H01L29/66621 , H01L29/7834
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a miniaturized trench gate MOS transistor.
SOLUTION: The method of forming a trench transistor includes steps of forming a trench 5 in a semiconductor substrate of a first conductivity type; forming a gate dielectric 20 in the trench 5; providing a first conductive filling material 30' in the trench 5 as gate electrode 30; forming a first source-and-drain region 4 by introducing impurities of a second conductive type into the surface of the substrate 1 alongside the trench 5; etching back the first conductive filling material 30' inside the trench 5 to set back to a given depth; introducing impurities of the second conductivity type into the surface of the substrate 1 in the interior of the trench 5 to form a second drain-and-source region 4'; forming insulating spacers 25, 25' on the first conductive filling material 30' inside the trench 5; and providing a second conductive filling material 30'' inside the trench 5 as an upper part of the gate electrode.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种形成小型化的沟槽栅极MOS晶体管的方法。解决方案：形成沟槽晶体管的方法包括在第一导电类型的半导体衬底中形成沟槽5的步骤; 在沟槽5中形成栅极电介质20; 在沟槽5中提供第一导电填充材料30'作为栅电极30; 通过将第二导电类型的杂质引入到沟槽5旁边的衬底1的表面中来形成第一源极和漏极区域4; 蚀刻沟槽5内部的第一导电填充材料30'以回到给定的深度; 将第二导电类型的杂质引入沟槽5的内部的衬底1的表面，以形成第二漏 - 源区域4'; 在沟槽5内部的第一导电填充材料30'上形成绝缘间隔件25,25'; 并且在沟槽5内部设置第二导电填充材料30“作为栅电极的上部。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2009117818A Method of manufacturing integrated circuit 审中-公开
标题翻译：制造集成电路的方法
公开(公告)号：JP2009117818A
公开(公告)日：2009-05-28
申请号：JP2008266581
申请日：2008-10-15
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： FAUL JUERGEN , GRAHAM ANDREW , POPP MARTIN , VERDUGO VICTOR , WU DONGPING
IPC分类号： H01L29/78 , H01L21/265 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L27/108
CPC分类号： H01L29/66621 , H01L21/26506 , H01L27/10876 , H01L29/4236
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an integrated circuit, which comprises different oxidation steps in forming different oxide layers covering different support regions or the bottom and the sidewalls of some trenches.
SOLUTION: The method of manufacturing the integrated circuit includes: a step of providing a semiconductor substrate 10 with a surface; a step of performing an ion implantation step, wherein at least one implant specifies is implanted especially near the first partial region 12 of the surface compared to the second partial region 14 of the surface; and a step of performing a single oxidation step to form a first oxide layer 32 with a first layer thickness covering the first partial region of the surface and a second oxide layer 36 with a second layer thickness covering the second partial region of the surface, wherein the first layer thickness differs from the second layer thickness.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造集成电路的方法，其包括在形成覆盖不同支撑区域或一些沟槽的底部和侧壁的不同氧化物层的不同氧化步骤。解决方案：集成电路的制造方法包括：向半导体衬底10提供表面的步骤; 执行离子注入步骤的步骤，其特征在于，与表面的第二部分区域14相比，特别是在表面的第一部分区域12附近植入至少一个植入物; 以及进行单一氧化步骤以形成覆盖表面的第一部分区域的第一层厚度的第一氧化物层32和覆盖表面的第二部分区域的第二层厚度的第二氧化物层36的步骤，其中第一层厚度与第二层厚度不同。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2009065120A Integrated circuit with mosfet including split work function gate 审中-公开
标题翻译：集成电路与MOSFET，包括分离工作功能门
公开(公告)号：JP2009065120A
公开(公告)日：2009-03-26
申请号：JP2008153334
申请日：2008-06-11
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： FAUL JUERGEN , SLESAZECK STEFAN , POPP MARTIN , WEIS ROLF
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/786
CPC分类号： H01L29/4983 , H01L27/10823 , H01L27/10838 , H01L27/10873 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a field-effect transistor with little gate induced drain leakage current and an integrated circuit which includes a thin insulator structure between a gate electrode and a source/drain region. SOLUTION: The gate electrode of a transistor 542 includes a main section 532 determining a first flat band voltage between the gate electrode and a channel region 512, and a first lateral section 535. The lateral section is in contact with the main section and determines a second flat band voltage between the gate electrode and first source/drain regions 514 and 516. The first and second flat band voltages differ by at least 0.1 eV. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有很小的栅极感应漏极漏电流的场效应晶体管和在栅极电极和源极/漏极区域之间包括薄绝缘体结构的集成电路。解决方案：晶体管542的栅极包括确定栅极电极和沟道区域512之间的第一平坦带电压的主要部分532和第一侧向部分535.侧向部分与主部分接触并且确定栅电极和第一源/漏区514和516之间的第二平带电压。第一和第二平带电压相差至少0.1eV。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2007059900A Connection structure and method of manufacturing the same 审中-公开
标题翻译：连接结构及其制造方法
公开(公告)号：JP2007059900A
公开(公告)日：2007-03-08
申请号：JP2006211817
申请日：2006-08-03
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： HEINECK LARS , POPP MARTIN
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a connection structure between a trench capacitor and an access transistor and to provide a method of manufacturing a connection structure corresponding to the same. SOLUTION: The connection structure connects a storage electrode of a trench capacitor formed at least partially in a semiconductor substrate and a selection transistor. The connection structure has: a portion of an intermediate layer disposed adjacent to the surface of the storage electrode; and an electrically conductive material disposed adjacent to the intermediate layer and electrically connected to a portion of the surface of the semiconductor substrate adjacent to the selection transistor wherein a part of the connecting structure is disposed on the semiconductor substrate so as to come near the horizontal surface of the substrate. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供沟槽电容器和存取晶体管之间的连接结构，并提供制造与其相对应的连接结构的方法。解决方案：连接结构连接至少部分地形成在半导体衬底中的沟槽电容器的存储电极和选择晶体管。连接结构具有：与存储电极的表面相邻设置的中间层的一部分; 以及与所述中间层相邻设置并与所述半导体衬底的与所述选择晶体管相邻的部分表面电连接的导电材料，其中所述连接结构的一部分设置在所述半导体衬底上以接近所述水平表面的基底。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2008263201A Integrated circuit with memory cell array and method for forming same 审中-公开
标题翻译：具有存储单元阵列的集成电路及其形成方法
公开(公告)号：JP2008263201A
公开(公告)日：2008-10-30
申请号：JP2008102660
申请日：2008-04-10
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： POPP MARTIN , SCHLOESSER TILL , SCHWERIN ULRIKE GRUENING VON , WEIS ROLF
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10817 , G11C5/063 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit with a memory cell array and a method for forming the same. SOLUTION: There are provided each bit line 61 extended along a first direction 62, each word line 60 extended along a second direction 63 crossing the first direction 62 substantially perpendicularly, each active region 40, and each bit line contact 57. Each bit line contact 57 is arranged in each column extended along the second direction 63 and in each row extended along the first direction 62. A distance dL between bit lines 61 adjacent each other and a distance dC parallel to the first direction 62 between bit line contacts 57 adjacent each other satisfy a relation 1/2.25≤dL/dC≤1/1.75. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有存储单元阵列的集成电路及其形成方法。解决方案：提供沿着第一方向62延伸的每个位线61，每条字线60沿着基本上垂直于第一方向62的第二方向63延伸，每个有源区40和每个位线接触57。位线接触件57布置在沿着第二方向63延伸的每列中，并且沿着第一方向62延伸的每列中。彼此相邻的位线61之间的距离dL和与位线触点之间的第一方向62平行的距离dC 57相互满足关系1 /2.25≤dL/dC≤1/ 1.75。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008072106A Memory cell array and method of forming the memory cell array 审中-公开
标题翻译：存储单元阵列和形成存储单元阵列的方法
公开(公告)号：JP2008072106A
公开(公告)日：2008-03-27
申请号：JP2007222134
申请日：2007-08-29
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： HEINECK LARS , POPP MARTIN
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L29/945 , H01L27/0207 , H01L27/10829 , H01L27/10861 , H01L27/10867 , H01L27/10876 , H01L27/10882 , H01L27/10891
摘要： PROBLEM TO BE SOLVED: To provide a DRAM memory cell array with a narrowed memory cell region. SOLUTION: Each memory cell includes a storage capacitor 3, an access transistor 16, a plurality of bit lines 2 oriented in a first direction, a plurality of word lines 8 oriented in a second direction, the second direction being perpendicular to the first direction, a semiconductor substrate 1 with a surface, and a plurality of active areas being formed in the semiconductor substrate, each active area extending in the second direction. Each of the access transistors is partially formed in the active areas and electrically couples corresponding ones of the storage capacitors to corresponding bit lines, wherein a gate electrode 19 of each of the access transistors is connected with a corresponding word line 8, a capacitor dielectric 38 of the storage capacitor has a relative dielectric constant of more than 8, and the word lines are disposed above the bit lines. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有变窄的存储单元区域的DRAM存储单元阵列。解决方案：每个存储单元包括存储电容器3，存取晶体管16，沿第一方向定向的多个位线2，沿第二方向定向的多个字线8，第二方向垂直于第一方向，具有表面的半导体衬底1和形成在半导体衬底中的多个有源区，每个有源区沿第二方向延伸。每个存取晶体管部分地形成在有源区域中并将对应的存储电容器电耦合到对应的位线，其中每个存取晶体管的栅极电极19与对应的字线8，电容器电介质38 的存储电容器的相对介电常数大于8，并且字线设置在位线上方。版权所有（C）2008，JPO＆INPIT

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