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1. 发明专利

JP2007027743A Integrated semiconductor structure and manufacturing method thereof 审中-公开
标题翻译：一体化半导体结构及其制造方法
公开(公告)号：JP2007027743A
公开(公告)日：2007-02-01
申请号：JP2006192767
申请日：2006-07-13
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： GOLDBACH MATTHIAS , WU DONGPING
IPC分类号： H01L21/8234 , H01L21/283 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L27/108 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823857
摘要： PROBLEM TO BE SOLVED: To provide an integrated semiconductor structure capable of adjusting the Fermi level of a P-MOS appropriately.
SOLUTION: A first transistor region T1 is an n-MOS region, a second transistor region T2 is a p-FET region, a base part dielectric layer 2 made of SiO
2 is formed on the first and second transistor regions, and an N+ polysilicon gate 4 is formed on the dielectric layer 2. The first region is protected by a mask, an aluminum ion is injected, and heat treatment is performed, thus forming a high-dielectric-constant interface dielectric layer 3 of AlxOv between the gate dielectric layer 2 and the N+ polysilicon gate 4, strengthening Fermi pinning effect, and hence adjusting a work function of the P-MOS of N+ polysilicon to a value close to the function of a P+ polysilicon gate.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够适当地调整P-MOS的费米能级的集成半导体结构。解决方案：第一晶体管区域T1是n-MOS区域，第二晶体管区域T2是p-FET区域，由SiO 2制成的基极介质层2形成在第一和第二晶体管区域，并且在电介质层2上形成N +多晶硅栅极4.第一区域被掩模保护，注入铝离子并进行热处理，从而形成高介电常数界面在栅极电介质层2和N +多晶硅栅极4之间的Al x O v的介电层3，强化费米钉扎效应，并因此将N +多晶硅的P-MOS的功函数调整到接近P +多晶硅栅极功能的值。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2009117818A Method of manufacturing integrated circuit 审中-公开
标题翻译：制造集成电路的方法
公开(公告)号：JP2009117818A
公开(公告)日：2009-05-28
申请号：JP2008266581
申请日：2008-10-15
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： FAUL JUERGEN , GRAHAM ANDREW , POPP MARTIN , VERDUGO VICTOR , WU DONGPING
IPC分类号： H01L29/78 , H01L21/265 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L27/108
CPC分类号： H01L29/66621 , H01L21/26506 , H01L27/10876 , H01L29/4236
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an integrated circuit, which comprises different oxidation steps in forming different oxide layers covering different support regions or the bottom and the sidewalls of some trenches.
SOLUTION: The method of manufacturing the integrated circuit includes: a step of providing a semiconductor substrate 10 with a surface; a step of performing an ion implantation step, wherein at least one implant specifies is implanted especially near the first partial region 12 of the surface compared to the second partial region 14 of the surface; and a step of performing a single oxidation step to form a first oxide layer 32 with a first layer thickness covering the first partial region of the surface and a second oxide layer 36 with a second layer thickness covering the second partial region of the surface, wherein the first layer thickness differs from the second layer thickness.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造集成电路的方法，其包括在形成覆盖不同支撑区域或一些沟槽的底部和侧壁的不同氧化物层的不同氧化步骤。解决方案：集成电路的制造方法包括：向半导体衬底10提供表面的步骤; 执行离子注入步骤的步骤，其特征在于，与表面的第二部分区域14相比，特别是在表面的第一部分区域12附近植入至少一个植入物; 以及进行单一氧化步骤以形成覆盖表面的第一部分区域的第一层厚度的第一氧化物层32和覆盖表面的第二部分区域的第二层厚度的第二氧化物层36的步骤，其中第一层厚度与第二层厚度不同。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2008022012A Transistor, memory cell, and its forming method 审中-公开
标题翻译：晶体管，存储单元及其形成方法
公开(公告)号：JP2008022012A
公开(公告)日：2008-01-31
申请号：JP2007184605
申请日：2007-07-13
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： WU DONGPING
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L29/66621 , H01L27/10876 , H01L27/10879 , H01L29/4236 , H01L29/66795 , H01L29/7851
摘要： PROBLEM TO BE SOLVED: To provide a forming method of a transistor comprising a step of defining an active region by defining its nearby element isolating trench and a step of forming a gate electrode after the element isolating trench is defined.
SOLUTION: The gate electrode is formed by a step of etching a gate groove in the active region selectively with respect to an insulating material filled in the element isolating trench, etching the insulating material filled in the element isolating trench in parts adjoining a channel such that the channel of a ridge-shape having an uppermost surface and two sides is not covered, a step of providing a gate insulating material on the uppermost surface and the two sides, and a step of providing a conductive material on the gate insulating material such that the gate electrode is arranged along the uppermost surface and the two sides of the channel.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种晶体管的形成方法，其包括通过限定其附近的元件隔离沟槽来限定有源区域的步骤，以及在限定元件隔离沟槽之后形成栅电极的步骤。解决方案：栅电极通过相对于填充在元件隔离沟槽中的绝缘材料选择性地蚀刻有源区中的栅极沟槽的步骤形成，在邻接元件隔离沟槽的部分中蚀刻填充在元件隔离沟槽中的绝缘材料通道，使得具有最上表面和两侧的脊形通道不被覆盖，在最上表面和两侧设置栅极绝缘材料的步骤，以及在栅极绝缘上提供导电材料的步骤材料，使得栅电极沿通道的最上表面和两侧布置。版权所有（C）2008，JPO＆INPIT

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