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1. 发明专利

JPS62160072A NONCONTROL TYPE DC/DC CONVERTER 失效
公开(公告)号：JPS62160072A
公开(公告)日：1987-07-16
申请号：JP137286
申请日：1986-01-09
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , TDK CORP
发明人： KOMORI ATSUSHI , KOJIMA SADAO , YAMANO SEIICHI , SHIMOZAWA KIYOSHI , SEKOGUCHI HIROSHI
IPC分类号： H02M3/28
摘要： PURPOSE:To prevent the secondary output voltage of a noncontrol type DC/DC converter from rising drastically and the primary circuit element from being deteriorated or burned out by stopping the switching of the converter when a voltage between input terminals is higher than a predetermined value. CONSTITUTION:A DC current applied to the primary side of a transformer 12 is switched by a switching element SW10, the secondary side output of the transformer 12 is smoothed by a rectifying and smoothing circuit 13, and supplied to a load RL. A voltage between the primary side input terminals L11 and L12 is monitored on an input voltage monitor 14 to stop the switching of the element SW10 when the voltage becomes higher than the predetermined value.

2. 发明专利

JPS59161155A Signal transmitting and receiving circuit 失效
标题翻译：信号发送和接收电路
公开(公告)号：JPS59161155A
公开(公告)日：1984-09-11
申请号：JP3447583
申请日：1983-03-04
申请人： Oki Electric Ind Co Ltd
发明人： KOJIMA SADAO , KISHINO MINORU
IPC分类号： H04B3/00 , H04B1/44 , H04B1/58 , H04L25/02 , H04L25/40
CPC分类号： H04B1/44 , H04B1/58
摘要： PURPOSE:To fetch a receiving signal when the current of the second winding is cut off, and to separate the signal satisfactorily from a transmitting signal by adding the third winding to the transformer of a signal transmitting and receiving circuit, and connecting a current source having a current intermittence control means to said winding through a transistor. CONSTITUTION:The first and the second windings 3A, 3B are provided on a transformer 3 of a signal transmitting and receiving circuit, and also the third winding 3C is added. The collector to which an NPN transistor TR21 and a PNP type TR22 are connected in common is connected to one end of this winding 3C, and the emitter connected in common through a resistor 23 is connected to the other end. Also, current sources 24, 25 having a current intermittence control means connected to control signal input terminals 13, 14 are connected to the bases of the TRs 21, 22. In this state, only in a period of time when a current of the winding 3B of the transformer 3 is cut off, a current is charged to the TRs 21, 22 from the current sources 24, 25, a receiving signal is outputted to receiving signal output terminals 50, 51 from both ends of the resistor 23, and this signal is separated satisfactorily from a transmitting signal.
摘要翻译：目的：当第二绕组的电流被切断时获取接收信号，并通过将第三绕组加到信号发射和接收电路的变压器上，将信号与发射信号分离，并连接具有通过晶体管对所述绕组的电流间歇控制装置。构成：第一绕组3A和第二绕组3B设置在信号发送和接收电路的变压器3上，并且还添加第三绕组3C。 NPN晶体管TR21和PNP型TR22共同连接的集电极连接到该绕组3C的一端，并且通过电阻器23共同连接的发射极连接到另一端。此外，具有连接到控制信号输入端子13,14的电流间歇控制装置的电流源24,25连接到TR 21,22的基极。在这种状态下，仅在绕组的电流的时间段变压器3的3B被截止，电流从电流源24,25向TR 21,22充电，接收信号从电阻器23的两端输出到接收信号输出端子50,51，这样信号从发送信号令人满意地分离。

3. 发明专利

JPS51120118A STATIONARY PICTURE RECORDING REPRODUCING DEVICE 失效
公开(公告)号：JPS51120118A
公开(公告)日：1976-10-21
申请号：JP4418675
申请日：1975-04-14
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KOJIMA SADAO , KOMORI ATSUSHI , SUZUKI MIKIO
IPC分类号： H04N5/907 , H04N5/76 , H04N7/00 , H04N7/14
摘要： PURPOSE:To prevent the deterioration of picture quality.

4. 发明专利

JPS5141946A FM HENCHOKI 失效
公开(公告)号：JPS5141946A
公开(公告)日：1976-04-08
申请号：JP11539274
申请日：1974-10-07
申请人： OKI ELECTRIC IND CO LTD
发明人： KOJIMA SADAO , KIMURA HARUFUSA
IPC分类号： H03K7/06 , H03K7/02

5. 发明专利

JPS60183836A TIME DIVISION MULTIPLEXING DEVICE 失效
公开(公告)号：JPS60183836A
公开(公告)日：1985-09-19
申请号：JP3875384
申请日：1984-03-02
申请人： OKI ELECTRIC IND CO LTD
发明人： SHIOJIMA MASANORI , KOJIMA SADAO
IPC分类号： H04J3/04 , H04J3/24 , H04Q11/04
摘要： PURPOSE:To enhance a degree of multiplexing to reduce the number of wirings and simplify the hard constitution by using an address bus for a multiplexing/ demultiplexing circuit to give an address number to each channel. CONSTITUTION:In an example of the constitution of a receiving part of a channel corresponding part (CH') 17', an address signal (i) of a pertinent channel (i) which is preliminarily set to each channel corresponding part (CH') 17'-i by an address setting circuit 26 and a reception address signal (RADD) 3' connected through a bus are compared with each other by a comparing circuit 27, and a write signal 24 is outputted to a buffer memory 25 when they coincide with each other. In this case, data to the channel corresponding part (CH') 17'-i corresponding to the channel (i) is sent to the bus to which an internal reception multiplex signal (RDATA) 2 is connected, and data is written in the buffer memory 25. Contents of the buffer memory 25 are read out in the original data speed to become a reproduced data signal 4-i. By the similar operation, transmission data 5-i is multiplexed into an internal transmission multiplex signal (SDATA) 6.

6. 发明专利

JPS59161156A Signal transmitting circuit 失效
标题翻译：信号发送电路
公开(公告)号：JPS59161156A
公开(公告)日：1984-09-11
申请号：JP3447683
申请日：1983-03-04
申请人： Oki Electric Ind Co Ltd
发明人： KOJIMA SADAO , KISHINO MINORU
IPC分类号： H04B3/00 , H04B1/44 , H04B1/58 , H04L25/02
CPC分类号： H04B1/58 , H04B1/44
摘要： PURPOSE:To fetch a receiving signal only in a period in which the current of the second winding is cut off, and to separate the signal from a transmitting signal by adding the third winding to the transformer of a signal transmitting and receiving circuit, connecting a transistor TR to this winding, and lowing the current to the TR from a current source having a current intermittence control means. CONSTITUTION:The first and the second windings 3A, 3B are provided on a transformer 3 of a signal transmitting and receiving circuit, and also the third winding 3C is added. Each collector of a pair of an NPN type transistor TR21 and a PNP type TR22 is connected to both ends of this winding 3C, and also each emitter is connected through a resistor 23. Also, current sources 24, 25 connected to control signal input terminals 13, 14 are connected to the respective bases of a pair of TRs 21, 22. A current is charged to the TRs 21, 22 from these current sources 24, 25, only in a period in which a current of the second winding 3B is cut off. In this state, a current is extracted from the bases of the TRs 21, 22, a receiving signal is outputted to both ends of the resistor 23, and the signal is separated satisfactorily from a transmitting signal.
摘要翻译：目的：仅在第二绕组的电流被切断的时间段内提取接收信号，并且通过将第三绕组加到信号发射和接收电路的变压器上来分离信号与发射信号，将晶体管TR到该绕组，并且从具有电流间歇控制装置的电流源降低到TR的电流。构成：第一绕组3A和第二绕组3B设置在信号发送和接收电路的变压器3上，并且还添加第三绕组3C。一对NPN型晶体管TR21和PNP型TR22的每个集电极连接到该绕组3C的两端，并且每个发射极通过电阻器23连接。而且，连接到控制信号输入端的电流源24,25 13,14连接到一对TRs 21,22的各个基极。仅在第二绕组3B的电流为第二绕组3B的电流的时段中，电流从这些电流源24,25被充电到TR 21,22。隔断。在这种状态下，从TRs21,22的基极提取电流，将接收信号输出到电阻器23的两端，并且信号从发送信号令人满意地分离。

7. 发明专利

JPS5685967A CONFERENCE TELEPHONE SYSTEM 失效
公开(公告)号：JPS5685967A
公开(公告)日：1981-07-13
申请号：JP16232679
申请日：1979-12-13
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： FUJII KENSAKU , IMAGAWA HITOSHI , KOJIMA SADAO , SHIRASAWA SUSUMU , OBARA SUSUMU
IPC分类号： H04M3/56
摘要： PURPOSE:To execute the conference telephone service with the same quality as the conventional service, by selecting 2 subscribers in order from the maximum voice level among all the subscribers, in the conference telephone system by which 3 or more subscribers are able to call at the same time. CONSTITUTION:When the conference is in a speech state, both the speaker's voice and other subscriber's background noise are input to the 2 subscriber sampling circuit 2, both the speaker's voice and the maximum background noise are selected and added, and the maximum background noise, the speaker's voice, and the voice and noise are sent out to the speaker, one subscriber to whom the noise has been selected, and other subscribers, respectively, by the distributing circuit 4. In case of the conversational state of 2 subscribers, the other speaker's voice is selected instead of the maximum background noise, its state becomes te regular telephone service between 2 subscribers, and othe subscribers are able to listen to the 2 subscriber's conversation. In the event of a cross state, the speaker himself hears other speaker's voice, and therefore, it can be known that 2 or more subscribers are speaking.

8. 发明专利

JPH0257743B2 失效
公开(公告)号：JPH0257743B2
公开(公告)日：1990-12-05
申请号：JP11653384
申请日：1984-06-08
申请人： OKI ELECTRIC IND CO LTD
发明人： SAKATA YOSHIO , HIROSE KUNIHARU , KOJIMA SADAO
IPC分类号： H04L7/08 , H04J3/06

9. 发明专利

JPS60261236A FRAME SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPS60261236A
公开(公告)日：1985-12-24
申请号：JP11653384
申请日：1984-06-08
申请人： OKI ELECTRIC IND CO LTD
发明人： SAKATA YOSHIO , HIROSE KUNIHARU , KOJIMA SADAO
IPC分类号： H04L7/08 , H04J3/06
摘要： PURPOSE:To reduce influences due to element delay, to use an element of TTL level and to lower power consumption by making frame synchronization after converting a high speed signal to a low speed signal. CONSTITUTION:A clock quartered by a quarter divider 1 of a frame synchronizing circuit is supplied to a serial/parallel converting circuit 2, and 140Mb/s data are converted to 34Mb/s data #1-#4 based on a clock from the frequency divider 1. The data are supplied to each of fixed frame synchronizing pattern detecting circuits 3-6, and predetermined frame patterns are detected separately. The frame pattern detection signal is outputted only when the circuits 3-6 detected all synchronous frames of 34Mb/s data in an AND gate 7. On the other hand, information from a frame counter 12 is supplied to an F pulse decoder 13, and outputs of the decoder 13 and data 7 are applied to an AND gate 8. Dissident pulses of the gate 8 are processed by a synchronism protecting circuit 9, and gates 10, 11 and a timer 14, and influences due to element delay are reduced.

10. 发明专利

JPS5880916A INTERFACE CIRCUIT 失效
公开(公告)号：JPS5880916A
公开(公告)日：1983-05-16
申请号：JP17868781
申请日：1981-11-07
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , OKI ELECTRIC IND CO LTD , FUJITSU LTD
发明人： HAMASATO KAZUO , OONO MASAHIKO , SAKURAI YOSHITO , KOJIMA SADAO , TAKADA KENZOU
IPC分类号： H04B3/00 , G06G7/12 , H03H11/02
摘要： PURPOSE:To apply a process of manufacturing an integrated circuit with low dielectric strength to one interface circuit, and to realize reduction in chip area and economization, by applying current coupling to an information coupling means from one side to the other. CONSTITUTION:The input SIGi of an interface circuit INT is connected to one input of a control circuit CONT, whose output is connected to the input CPUi of a coupling means CPU; and the output CPUo of the coupling means CPU is connected to the input CSi of a current generating means CS, whose one output CS01 is connected to the output SIGo of the interface circuit INF while the other output CS00 is connected to the other input of the control circuit CONT. The control circuit CONT executes a comparison between those two input signals, i.e. SIGi and CS00 and performs control to obtain coincidence between both of them, so both inputs are in proportion to each other in a balanced state and both outputs CS01 and CS00 of the current generating means CS have proportional relation, so that the inputs SIGi to the interface circuit INF and the output SIGo are in proportion to each other.

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