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1. 发明专利

JP2004200600A Wafer-flatness evaluation method and device for implementing the evaluation method; wafer production method using the evaluation method, wafer-quality ensuring method using the evaluation method, semiconductor device production method using the evaluation method, and semiconductor device production method using the wafer evaluated by the evaluation method 有权
公开(公告)号：JP2004200600A
公开(公告)日：2004-07-15
申请号：JP2002370502
申请日：2002-12-20
申请人： Nikon Corp , Shin Etsu Handotai Co Ltd , Toshiba Corp , 信越半導体株式会社 , 株式会社ニコン , 株式会社東芝
发明人： FUJISAWA TADAHITO , INOUE SOICHI , KOBAYASHI MAKOTO , ICHIKAWA MASASHI , HAGIWARA TSUNEYUKI , KODAMA KENICHI
IPC分类号： H01L21/66 , G01B11/30 , H01L21/027 , H01L21/302 , H01L21/461
CPC分类号： G01B21/30 , G01B11/306 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a wafer-flatness evaluation method whereby the flatnesses present in the surface of a wafer can be evaluated in the state closer to a flatnesses which an exposure device can sense. SOLUTION: The wafer-flatness evaluation method has a process (300) for measuring the front and rear surface shapes of a wafer, a process (301) for partitioning the front and rear surfaces of the wafer into their sites, processes (302, 303, 304, 305) for selecting wafer-flatness calculating ways in response to the positions of the valuing sites, and a process (306) for acquiring the flatnesses present in the surface of the wafer. COPYRIGHT: (C)2004,JPO&NCIPI

2. 发明专利

JP2007273560A Light intensity distribution simulation method 审中-公开
标题翻译：光强分布模拟方法
公开(公告)号：JP2007273560A
公开(公告)日：2007-10-18
申请号：JP2006094847
申请日：2006-03-30
申请人： Toshiba Corp , 株式会社東芝
发明人： TANAKA SATOSHI , SANHONGI SHOJI , SATO TAKASHI , INOUE SOICHI
IPC分类号： H01L21/027 , G03F7/20
CPC分类号： G06F17/5009
摘要： PROBLEM TO BE SOLVED: To provide a light intensity distribution simulation method easily reflecting the effect of the thickness of a pattern film of a photomask on a calculation result. SOLUTION: The light intensity distribution simulation method includes a step of extracting a plurality of point light sources (SX, SY); a step of causing light ψ emitted from each of the point light sources (SX, SY) to fall to a pattern film 100 having openings 101a, 101b, and 101c; a step of calculating effective shapes of the openings 101a, 101b, and 101c by subtractors, on which the light ψ is not directly incident due to the side wall of the pattern film 100 from the designed shapes of the openings 101a, 101b, and 101c; and a step of calculating the light intensity distribution of diffracted light that is generated by the light ψ at the openings 101a, 101b, and 101c and is weakened due to an area difference between the designed shape and the effective shape. Calculation is made on the assumption that the pattern film 100 has no thickness. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：为了提供容易地反映光掩模图案膜的厚度对计算结果的影响的光强度分布模拟方法。光强分布模拟方法包括提取多个点光源（SX，SY）的步骤; 使从每个点光源（SX，SY）发射的光ψ落到具有开口101a，101b和101c的图案膜100上的步骤; 通过减法器计算开口101a，101b和101c的有效形状的步骤，其中光ψ由于开口101a，101b和101c的设计形状而不由于图案膜100的侧壁而直接入射 ; 以及计算由开口101a，101b和101c处的光ψ产生的衍射光的光强度分布的步骤，并且由于设计形状和有效形状之间的面积差而变弱。假设图案膜100没有厚度进行计算。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2006210856A Exposure method and manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的曝光方法和制造方法
公开(公告)号：JP2006210856A
公开(公告)日：2006-08-10
申请号：JP2005024553
申请日：2005-01-31
申请人： Toshiba Corp , 株式会社東芝
发明人： KIYOU SUIGEN , INOUE SOICHI
IPC分类号： H01L21/027 , G03F7/20
摘要： PROBLEM TO BE SOLVED: To suppress microscopic deviation of distribution of light quantity, in bridging exposure using a filter. SOLUTION: An exposure device comprising a filter which includes a transmitting region almost uniform in the quantity of transmitting light and shielding regions so formed as to sandwich the transmitting region, an original plate for bridging exposure, a stage on which a substrate is mounted, and light quantity varying means for varying the light quantity on the substrate by a specified width, is prepared. When an optical positional relationship between the original plate and the substrate is a first condition, and a pattern formed in a first original plate region is transferred to a first substrate region. A pattern formed in a second original plate region under the first condition is transferred to a second substrate region. When the optical positional relationship between the original plate and the substrate is a second condition, a pattern formed in a third original plate region is transferred to a third substrate region overlapping with the first substrate region by the specified width. A pattern formed in a fourth original plate region under the second condition is transferred to a fourth substrate region overlapping with the second substrate region by the specified width. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在使用过滤器的桥接曝光中，抑制光量分布的微观偏差。解决方案：一种曝光装置，包括滤光器，该滤光器包括透射光量几乎均匀的透射区域和形成为夹着透射区域的屏蔽区域，用于桥接曝光的原版板，基板上的基板并且准备用于将基板上的光量改变指定宽度的光量变化装置。当原版和基板之间的光学位置关系是第一条件时，在第一原版区域中形成的图案被转印到第一基板区域。在第一条件下在第二原版区域中形成的图案被转印到第二基板区域。当原版和基板之间的光学位置关系为第二条件时，形成在第三原版区域中的图案被转印到与第一基板区域重叠指定宽度的第三基板区域。在第二条件下形成在第四原版区域中的图案被转移到与第二基板区域重叠指定宽度的第四基板区域。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005338650A Data generation method for pattern and pattern verification method 有权
标题翻译：用于模式和模式验证方法的数据生成方法
公开(公告)号：JP2005338650A
公开(公告)日：2005-12-08
申请号：JP2004160127
申请日：2004-05-28
申请人： Toshiba Corp , 株式会社東芝
发明人： NOJIMA SHIGEKI , TANAKA SATOSHI , KOTANI TOSHIYA , DEWA KYOKO , INOUE SOICHI
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G06F17/50 , G21K5/10 , H01L21/027 , G03F1/08
CPC分类号： G03F1/36
摘要： PROBLEM TO BE SOLVED: To provide a data generation method for a pattern by which a specified pattern can be formed even when various fluctuations are present in the process. SOLUTION: The method includes steps of: preparing an integrated circuit design pattern including a design pattern; setting the range of allowable fluctuation in a first pattern formed on a substrate by transferring the design pattern and in a second pattern formed by processing the substrate by using the first pattern as a mask; generating a target pattern within the determined allowable fluctuation range; and correcting the target pattern under specified conditions considering influences of transferring and/or forming the design pattern on the substrate to generate a first corrected pattern. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供即使在该过程中存在各种波动的情况下也可以形成指定图案的图案的数据生成方法。解决方案：该方法包括以下步骤：制备包括设计图案的集成电路设计图案; 通过转印设计图案和通过使用第一图案作为掩模将基板加工形成的第二图案设置在形成在基板上的第一图案中的允许波动的范围; 在确定的容许波动范围内产生目标图案; 并且考虑在衬底上转移和/或形成设计图案以产生第一校正图案的影响的规定条件下校正目标图案。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2005284272A Method for correcting mask pattern, method for verifying mask pattern, method for manufacturing photomask, and method for manufacturing semiconductor device 审中-公开
标题翻译：用于校正掩模图案的方法，用于验证掩模图案的方法，用于制造光刻胶的方法以及制造半导体器件的方法
公开(公告)号：JP2005284272A
公开(公告)日：2005-10-13
申请号：JP2005057805
申请日：2005-03-02
申请人： Toshiba Corp , 株式会社東芝
发明人： KOTANI TOSHIYA , TANAKA SATOSHI , NOJIMA SHIGEKI , HASHIMOTO KOJI , INOUE SOICHI
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G06F17/50 , H01L21/027 , H01L21/336 , H01L21/82 , H01L21/8234 , H01L27/088 , H01L29/78 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To improve correction efficiency for correcting deviation in a pattern dimension and to reduce the process time for correcting a mask pattern. SOLUTION: The method for correcting a pattern for correcting a design pattern so as to form a desired pattern on a wafer includes steps of: specifying a allowable dimensional deviation in each design pattern; specifying conditions for pattern correction for each design pattern based on the above allowable dimensional deviation specified to each pattern; and correcting each design pattern based on the conditions for pattern correction specified for each design pattern. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提高用于校正图案尺寸的偏差的校正效率并且减少用于校正掩模图案的处理时间。解决方案：用于校正用于校正设计图案以在晶片上形成期望图案的图案的方法包括以下步骤：指定每种设计图案中的允许尺寸偏差; 基于针对每个图案指定的上述允许尺寸偏差来指定每个设计图案的图案校正条件; 并且基于针对每个设计图案指定的图案校正的条件来校正每个设计图案。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2004117728A Mask, manufacturing method of the same, and manufacturing method of semiconductor device 有权
公开(公告)号：JP2004117728A
公开(公告)日：2004-04-15
申请号：JP2002279742
申请日：2002-09-25
申请人： Toshiba Corp , 株式会社東芝
发明人： DEWA KYOKO , KANAI HIDEKI , INOUE SOICHI , KANEMITSU SHINGO , ITO SHINICHI
IPC分类号： G03F1/26 , G03F1/38 , G03F7/20 , G03F9/00 , G03F9/02 , H01L21/027 , G03F1/08
CPC分类号： G03F1/30 , G03F1/32 , G03F7/70641 , G03F7/70683
摘要： PROBLEM TO BE SOLVED: To provide a mask and a manufacturing method of the same for suppressing increase of manufacturing processes, etc. SOLUTION: The mask comprises a first area 10 including a first peripheral part at which a halftone film 102 or a laminated film of the halftone film 102 and a light shield film 103 is formed on a translucent substrate 101 and a first opening part surrounded by the first peripheral part; and a second area 20 including a second peripheral part at which the halftone film 102 is formed on the translucent substrate 101 and a second opening part surrounded by the second peripheral part, and is configured to form a translucent film 106 on at least a portion of the second opening part and generate a prescribed phase difference between an exposure light passing through an area corresponding to a portion at which a translucent film of the second opening part and an exposure light passing through the second peripheral part. COPYRIGHT: (C)2004,JPO

7. 发明专利

JP2004108820A Method for evaluating photomask, and program 有权
公开(公告)号：JP2004108820A
公开(公告)日：2004-04-08
申请号：JP2002268659
申请日：2002-09-13
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMAGUCHI SHINJI , INOUE SOICHI , INOUE MARI
IPC分类号： G01N21/956 , G03F1/68 , G03F1/70 , H01L21/027 , H01L21/66 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To achieve a practical yield prediction method of photomasks by using a critical area analysis.
SOLUTION: Defect inspection information used for inspecting defects on photomasks is reflected on design data in mask patterns and a critical area is calculated to the design data (step S1). A defect density distribution to the number of defects per unit area on the photomasks to the size of defects on the photomasks is estimated (step S2). The critical area and the defect density distribution are estimated and the number of killer defects on the photomasks is acquired (steps S3, S4). The yield of the photomasks is predicted based on the number of killer defects (step S5).
COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2004039860A Method for monitoring light exposure and method for manufacturing semiconductor device 有权
公开(公告)号：JP2004039860A
公开(公告)日：2004-02-05
申请号：JP2002194927
申请日：2002-07-03
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJISAWA TADAHITO , INOUE SOICHI , SATO TAKASHI , ASANO MASASHI
IPC分类号： H01L21/027 , G03F7/20 , G03F7/207
CPC分类号： G03F7/70558
摘要： PROBLEM TO BE SOLVED: To easily achieve a required exposure sensitivity level by relaxing light exposure monitoring pattern design conditions.
SOLUTION: In this exposure monitoring method, illuminating light is projected upon a mask with an exposure monitoring pattern formed thereon, only zero-order diffracted light out of the diffracted light in the exposure monitoring pattern is made to pass in the pupil plane 200 of the projection aligner, and the exposure monitoring pattern is transferred to a substrate. During the projection of illuminating light, the centroid of a zero-order optical figure 211 after passing the exposure monitoring pattern on the pupil plane 200 of the projection aligner is deviated from an optical axis OA.
COPYRIGHT: (C)2004,JPO

9. 发明专利

JP2010251385A Pattern forming method 有权
标题翻译：图案形成方法
公开(公告)号：JP2010251385A
公开(公告)日：2010-11-04
申请号：JP2009096488
申请日：2009-04-10
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKAHASHI MASANORI , TANAKA SATOSHI , INOUE SOICHI , SANHONGI AKIKO , KODERA KATSUMASA , TAKAGI TAKAMASA
IPC分类号： H01L21/027 , G03F1/00 , G03F1/68 , G03F7/20
CPC分类号： G03F1/36
摘要： PROBLEM TO BE SOLVED: To provide a pattern forming method for easily forming various kinds of patterns which are finer compared with an upper layer pattern. SOLUTION: The pattern forming method for forming the pattern onto a substrate includes: a resist layer laminating step of laminating a resist layer 3X on the upper layer side of a pattern formation layer 4X to be used for forming a desired pattern on the substrate; a diffraction pattern forming step of forming a diffraction pattern 1A having an opening opened at a predetermined pitch p for diffracting exposure light on the upper layer side of the resist layer 3X; and a whole image exposure step of performing whole image exposure with respect to the resist layer 3X in which a refractive index with respect to the exposure light is n, with diffracted light acquired by irradiation of exposure light having a wavelength λ from above the diffraction pattern 1A, which is then diffracted by the diffraction pattern 1A. The predetermined pitch p of the diffraction pattern 1A, the wavelength λ of the exposure light, and the refractive index n satisfy a condition of p>λ/n. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于容易地形成与上层图案相比更精细的各种图案的图案形成方法。解决方案：用于在基板上形成图案的图案形成方法包括：抗蚀剂层层压步骤，在图案形成层4X的上层侧层叠抗蚀剂层3X，以在图案形成层4X上形成所需图案基质; 衍射图案形成步骤，形成具有以预定间距p开口的开口的衍射图案1A，用于在抗蚀剂层3X的上层侧衍射曝光光; 以及对于相对于曝光光的折射率为n的抗蚀剂层3X进行全部图像曝光的整体图像曝光步骤，通过从衍射图案的上方照射具有波长λ的曝光光而获得的衍射光 1A，然后用衍射图1A衍射。衍射图案1A的预定间距p，曝光光的波长λ和折射率n满足p>λ/ n的条件。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2010211117A Pattern correction device and pattern correction method 审中-公开
标题翻译：图案校正装置和图案校正方法
公开(公告)号：JP2010211117A
公开(公告)日：2010-09-24
申请号：JP2009059456
申请日：2009-03-12
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUNAWA TETSUAKI , INOUE SOICHI
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , H01L21/027
CPC分类号： G06K9/036 , G03F1/36
摘要： PROBLEM TO BE SOLVED: To provide a pattern correction device capable of quickly and accurately performing correction processing of a pattern for use in manufacturing a semiconductor device.
SOLUTION: The pattern correction device includes: a pattern shape variable mask 12 formed by arranging a plurality of dot-shaped cells capable of varying transmittance or reflectance; a photodetector part 14 which is formed by arranging a plurality of dot-shaped optical sensor cells for detecting light and detects an optical image of a mask pattern formed by the pattern shape variable mask 12; a projection optical system 13 which forms an image of light radiated from a lighting part 11 to the pattern shape variable mask 14, on the photodetector part 14; and a control part 23 which controls cells of the pattern shape variable mask 12 in accordance with a shape of design layout to form a mask pattern and determines a correction amount of the mask pattern so that the difference between the optical image obtained in the photodetector part 14 by light radiated to the mask pattern and the design layout is within a prescribed range.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供能够快速且准确地执行用于制造半导体器件的图案的校正处理的图案校正装置。解决方案：图案校正装置包括：通过布置能够改变透射率或反射率的多个点状单元形成的图案形状可变掩模12; 通过布置多个用于检测光的点状光学传感器单元并检测由图案形状可变掩模12形成的掩模图案的光学图像而形成的光电检测器部分14; 投影光学系统13，其在光电检测器部分14上形成从照明部分11辐射到图案形状可变掩模14的光的图像; 以及控制部23，其根据设计布局的形状来控制图案形状可变掩模12的单元，以形成掩模图案，并确定掩模图案的校正量，使得在光电检测器部分中获得的光学图像之间的差异通过照射到掩模图案的光，并且设计布局在规定的范围内。版权所有（C）2010，JPO＆INPIT

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