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1. 发明专利

JP2012069863A Wiring board and manufacturing method therefor 有权
标题翻译：接线板及其制造方法
公开(公告)号：JP2012069863A
公开(公告)日：2012-04-05
申请号：JP2010215256
申请日：2010-09-27
申请人： Nec Corp , Nec Toppan Circuit Solutions Inc , 日本電気株式会社 , 株式会社トッパンNecサーキットソリューションズ
发明人： KIKUCHI KATSU , YAMAMICHI SHINTARO , MURAI HIDEYA , MORI KENTARO , NAKAJIMA YOSHIKI , OSHIMA DAISUKE , AKIMOTO YUTAKA , ISHIOKA TAKU
IPC分类号： H05K3/46 , H01L23/12
CPC分类号： H01L2224/04105 , H01L2224/18 , H01L2224/24195 , H01L2224/73267 , H01L2224/92244 , H01L2924/19105 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a thin wiring board excellent in rigidity, having an embedded electronic component.SOLUTION: The wiring board having the embedded electronic component includes: a base insulation layer; a pedestal pattern disposed on the upper face side of the base insulation layer; an electronic component on the pedestal pattern; a reinforcement insulation layer surrounding the outer circumference of the electronic component; a core wiring structure layer disposed on the reinforcement insulation layer and including a core insulation layer, having an opening having the electronic component disposed inside, upper face-side core wiring and lower face-side core wiring; an embedded insulation layer disposed on the core wiring structure layer in a manner to embed the electronic component; and first wiring on the substrate upper face side and second wiring on the substrate lower face side electrically connected to the electronic component. The outer edge of the pedestal is placed on the outer side than the outer edge of the electronic component. The reinforcement insulation layer includes a first reinforcement fiber, which is disposed from the peripheral area of the pedestal pattern outer than the outer edge to right above the outer edge of the pedestal pattern.
摘要翻译：要解决的问题：提供具有嵌入式电子部件的刚性优异的薄布线基板。解决方案：具有嵌入式电子部件的布线基板包括：基底绝缘层; 设置在所述基底绝缘层的上表面侧的基座图案; 基座图案上的电子部件; 围绕电子部件的外周的加强绝缘层; 芯线布线结构层，设置在所述加强绝缘层上并且包括芯绝缘层，具有设置在所述电子部件内部的开口，上表面侧芯线布线和下表面侧芯线布线; 嵌入绝缘层，以嵌入电子部件的方式设置在芯线布线结构层上; 并且在基板上表面侧的第一布线和与电子部件电连接的基板下表面侧的第二布线。基座的外边缘位于电子部件的外边缘的外侧。所述加强绝缘层包括第一加强纤维，所述第一加强纤维从所述基座图案的周边区域设置在所述基座图案的外边缘的外边缘的外侧。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2006190885A Substrate for layer formation, wiring substrate and its manufacturing method, and semiconductor device and its manufacturing method 有权
标题翻译：用于层形成的基板，布线基板及其制造方法及半导体器件及其制造方法
公开(公告)号：JP2006190885A
公开(公告)日：2006-07-20
申请号：JP2005002659
申请日：2005-01-07
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , KIKUCHI KATSU , YAMAMICHI SHINTARO , ORITO NAONORI , NAKANO KAICHIRO , MAEDA KATSUMI , TANAKA DAISUKE , SOEJIMA KOJI , KURITA YOICHIRO
IPC分类号： H01L23/12 , H01L23/32
CPC分类号： H01L2224/16
摘要： PROBLEM TO BE SOLVED: To provide a substrate for layer formation capable of easily separating a wiring layer and stably forming a wiring layer, a wiring substrate and its manufacturing method, and to provide a semiconductor device and its manufacturing method. SOLUTION: There is formed an exfoliation layer composed of resin which contains an elastomer on a support substrate. After forming copper wiring 3 on the exfoliation layer, a via 5 is formed on the copper wiring 3 so that an insulating film 4 may be formed for covering portions other than the upper surface of the via 5. Furthermore, copper wiring 6 connected electrically to the copper wiring 3 through the via 5 is formed on the insulating film 4. Moreover, after forming a via 8 on the copper wiring 6 so that an insulating layer 7 may be formed for covering portions other than the upper surface of the via 8, copper wiring 9 connected electrically to the copper wiring 6 and the via 8 is formed on the insulating film 7. After the support board 1 wherein a wiring layer 11 and a wiring layer 12 are formed is carried out by plasma polymerization in gas containing a fluoridation carbon gas so as to reduce the adhesion power of the exfoliation layer, a wiring substrate 10 is obtained by separating the wiring layer 11 and the wiring layer 12. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够容易地分离布线层并稳定地形成布线层的层形成用基板，布线基板及其制造方法，提供半导体装置及其制造方法。解决方案：在支撑基板上形成包含弹性体的由树脂构成的剥离层。在剥离层上形成铜布线3之后，在铜布线3上形成通孔5，以形成绝缘膜4，以覆盖通孔5的上表面以外的部分。此外，铜布线6电连接到在绝缘膜4上形成通过通孔5的铜布线3.此外，在铜布线6上形成通孔8之后，可以形成用于覆盖通孔8的上表面以外的部分的绝缘层7，在绝缘膜7上形成有与铜布线6和通路8电连接的铜布线9.在其中形成布线层11和布线层12的支撑板1之后，通过在含氟化物的气体中进行等离子体聚合碳气体，以降低剥离层的附着力，通过分离布线层11和布线层12获得布线基板10.（C）2006，JPO＆NCIPI

3. 发明专利

JP2006179952A Manufacturing method of wiring board for mounting semiconductor, and manufacturing method of semiconductor apparatus 有权
标题翻译：用于安装半导体的接线板的制造方法和半导体器件的制造方法
公开(公告)号：JP2006179952A
公开(公告)日：2006-07-06
申请号：JP2006068413
申请日：2006-03-13
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , ORITO NAONORI , FUNAYA TAKUO , KIKUCHI KATSU , YAMAMICHI SHINTARO , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO , MATSUI KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/12
CPC分类号： H01L2224/48091 , H01L2224/48227 , H01L2924/15312 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide manufacturing methods of a wiring board for mounting a semiconductor and of a semiconductor apparatus which are effective for the increase in terminals and the fine-pitch of terminal gaps due to high-integration, high-speed, and multi-functionalization of semiconductor devices, can mount semiconductor devices especially on both surfaces of a board in a high density and with a high precesion, and is further excellent in reliability. SOLUTION: The wiring board 5 comprises at least an insulation film 1, wiring 2 formed in the insulation film 1, and a plurality of electrode pads 4 which are made mutually conductive by the wiring 2 and vias 3. The electrode pads 4 are disposed on the front and back surfaces of the insulation film 1 with the surfaces of the pads exposed and at least a part of the sides of the electrode pads embedded in the insulation film 1. The insulation film 1 is formed by forming respective electrode pads 4 on two metal sheets, stacking insulation layers and wiring on the electrode pads 4 and the metal plates, laminating, and integrating the insulation layers, and then removing the metal sheets. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供用于安装半导体的布线板和半导体装置的制造方法，其对于增加端子和由于高集成度而导致的端子间隙的微细间距高效率和半导体器件的多功能化，可以以高密度和高密度安装半导体器件，特别是在板的两个表面上，并且其可靠性更好。解决方案：布线板5至少包括绝缘膜1，形成在绝缘膜1中的布线2和由布线2和通孔3相互导电的多个电极焊盘4.电极焊盘4 设置在绝缘膜1的前表面和后表面上，其中焊盘的表面暴露，并且电极焊盘的至少一部分侧面嵌入绝缘膜1中。绝缘膜1通过形成相应的电极焊盘 4的两个金属片，堆叠绝缘层和电极焊盘4和金属板上的布线，层压并整合绝缘层，然后去除金属片。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2007250712A Semiconductor device and method of manufacturing same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007250712A
公开(公告)日：2007-09-27
申请号：JP2006070347
申请日：2006-03-15
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , HONDA KOICHI , KIKUCHI KATSU , SOEJIMA KOJI , KYOGOKU YOSHITAKA , YAMAMICHI SHINTARO
IPC分类号： H01L21/60 , H01L23/12
CPC分类号： H01L2224/13
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device excellent in reliability in which breakage of a joint is prevented by relaxing thermal stress resulting from difference in thermal expansion coefficient between a substrate and a semiconductor chip, efficiently and to provide a method of manufacturing the same. SOLUTION: In the semiconductor device where a substrate 21 provided with a plurality of second pads 23 on the semiconductor chip mounting side, and a semiconductor chip 11 having a resin layer 12 provided on the surface and a plurality of first pads 13 provided on the resin layer 12 are connected electrically by flip-chip connection, at least one of the first pads 13 of the semiconductor chip 11 inclines or deforms and the distance between the first pad 13 and the surface of the semiconductor chip 11 is set longer at the peripheral side end of the semiconductor chip 11 than at the central end of the semiconductor chip 11. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可靠性优异的半导体器件，其通过缓解由基板和半导体芯片之间的热膨胀系数的差异导致的热应力而防止接头断裂，并提供一种方法制造相同。解决方案：在半导体器件中，在半导体芯片安装侧设置有多个第二焊盘23的基板21和设置在表面上的树脂层12的半导体芯片11和设置有多个第一焊盘13的半导体装置在树脂层12上通过倒装芯片连接电连接，半导体芯片11的至少一个第一焊盘13倾斜或变形，第一焊盘13与半导体芯片11的表面之间的距离设定得更长半导体芯片11的外围侧端部比半导体芯片11的中心端。（C）2007年，JPO＆INPIT

5. 发明专利

JP2007096337A Wiring substrate for mounting semiconductor, semiconductor package, and its manufacturing method 审中-公开
标题翻译：用于安装半导体的接线基板，半导体封装及其制造方法
公开(公告)号：JP2007096337A
公开(公告)日：2007-04-12
申请号：JP2006313640
申请日：2006-11-20
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , ORITO NAONORI , FUNAYA TAKUO , KIKUCHI KATSU , YAMAMICHI SHINTARO , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO , MATSUI KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/12 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate for mounting semiconductor which is effective for the high integration of a semiconductor device, high speed, or increase in terminal by multifunction, and the narrow pitch of a distance between terminals, in which the semiconductor device can be mounted with high density and high accuracy specifically on the both surfaces of a substrate, and which is excellent also in reliability, its manufacturing method, and a semiconductor package.
SOLUTION: A wiring substrate 5 for mounting semiconductor is a wiring substrate comprising at least an insulating film 1, wiring 2 formed in the insulating film 1, and a plurality of electrode pads 4 conducted by the wiring 2 and a via 3. The electrode pad 4 is prepared on the front and back surfaces of the insulating film 1 such that the front surface is exposed. At least a part of the side surface of the electrode pad is embedded in the insulating film 1. The insulating film 1 can be formed by forming the electrode pads 4 on two sheets of metal plates, laminating the insulating layer and the wiring on the electrode pad 4 and each metal plate, pasting the insulating layer together and unifying the layer, and removing the metal plate.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体装置的布线基板，其有效用于半导体器件的高集成度，高速度或多功能的端子增加，以及端子之间的距离的窄间距，其中半导体器件可以特别地在基板的两个表面上高密度和高精度地安装，并且在可靠性，其制造方法和半导体封装中也是优异的。解决方案：用于安装半导体的布线基板5是至少包括绝缘膜1，形成在绝缘膜1中的布线2和由布线2和通孔3传导的多个电极焊盘4的布线基板。在绝缘膜1的前表面和后表面上制备电极焊盘4，使得前表面露出。电极焊盘的侧面的至少一部分嵌入在绝缘膜1中。绝缘膜1可以通过在两片金属板上形成电极焊盘4而形成，在电极上层压绝缘层和布线垫4和每个金属板，将绝缘层粘贴在一起并使层合并，并移除金属板。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006228919A Wiring board, semiconductor device, and their manufacturing method 有权
标题翻译：接线板，半导体器件及其制造方法
公开(公告)号：JP2006228919A
公开(公告)日：2006-08-31
申请号：JP2005040062
申请日：2005-02-17
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： KIKUCHI KATSU , YAMAMICHI SHINTARO , MURAI HIDEYA , ORITO NAONORI , NAKANO KAICHIRO , MAEDA KATSUMI , TANAKA DAISUKE , KURITA YOICHIRO , SOEJIMA KOJI
IPC分类号： H05K3/20 , H01L23/12 , H01L23/14
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2924/01322 , H01L2924/15192 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a wiring board wherein a water system process is used to stably form a wiring structural body on a supporting substrate, and the wiring structural body can be easily peeled off from the supporting substrate. SOLUTION: The wiring board 10 includes a supporting substrate 11 and a wiring structural body 17 which is arranged on the supporting substrate 11 with an adhesion layer 24 in-between. The adhesion layer 24 is comprised of a first layer 12 made of a water-soluble material, and a second layer 13 which is formed so as to cover the entire surface of the first layer 12 and is made of a waterproof material. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种布线板，其中使用水系统工艺来在支撑基板上稳定地形成布线结构体，并且布线结构体可以容易地从支撑基板剥离。解决方案：布线板10包括支撑基板11和布置在支撑基板11上的布线结构体17，其间具有粘合层24。粘合层24由水溶性材料制成的第一层12和形成为覆盖第一层12的整个表面并由防水材料制成的第二层13构成。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2006032600A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006032600A
公开(公告)日：2006-02-02
申请号：JP2004208375
申请日：2004-07-15
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： KIKUCHI KATSU , YAMAMICHI SHINTARO , MURAI HIDEYA , HONDA KOICHI , SOEJIMA KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/522 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/12 , H01L23/52 , H01L27/04
CPC分类号： H01L23/528 , H01L23/3114 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has an enormous wiring structure to mitigate stress generated in a fine wiring structure, and operates at a large drive current and a high frequency with high reliability.
SOLUTION: A fine wiring structure 12 by laminating a first wiring layer and a first insulating layer alternately is provided on a semiconductor substrate 11, and a first enormous wiring structure 13a is provided by laminating a second wiring layer 15 having a thickness which is twice or more the first wiring layer and a second insulating layer 14, alternately. Further, a second enormous wiring structure 13b is provided on the first enormous wiring structure 13a by laminating a third wiring layer 17 having a thickness which is twice or more the first wiring layer and a third insulating layer 16 having an elastic modulus smaller than the second insulating layer 14 at 25 °C alternately. Thus, stress generated in the semiconductor device after being mounted to a mounting board is effectively mitigated in the first enormous wiring structure 13a and the second enormous wiring structure 13b, and stress applied to the fine wiring structure 12 can be reduced.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有巨大布线结构以减轻精细布线结构中产生的应力的半导体器件，并以高可靠性的大驱动电流和高频工作。解决方案：通过在半导体衬底11上设置层叠第一布线层和第一绝缘层的精细布线结构12，并且通过层叠具有厚度的第二布线层15来提供第一巨大布线结构13a 是第一布线层和第二绝缘层14的两倍以上。此外，通过层叠第一布线层的两倍以上的厚度的第三布线层17和弹性模量小于第二布线层的第三绝缘层16，在第一布线结构13a上设置第二大布线结构13b 绝缘层14交替地在25℃。因此，在第一巨大布线结构13a和第二巨大布线结构13b中，在安装到安装板上之后在半导体器件中产生的应力被有效地减轻，并且可以减小施加到精细布线结构12的应力。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005039260A Stress relaxation structure and formation method therefor, stress relaxation sheet and manufacturing method therefor, and semiconductor device and electronic equipment 有权
标题翻译：应力松弛结构及其形成方法，应力松弛片及其制造方法及半导体器件及电子设备
公开(公告)号：JP2005039260A
公开(公告)日：2005-02-10
申请号：JP2004192446
申请日：2004-06-30
申请人： Nec Corp , 日本電気株式会社
发明人： MURAI HIDEYA , KIKUCHI KATSU , ORITO NAONORI , BABA KAZUHIRO
IPC分类号： H01L23/12
CPC分类号： H01L2224/16225 , H01L2924/15174
摘要： PROBLEM TO BE SOLVED: To provide a stress relaxation structure and its formation method that is superior in stress relaxation effects upon thermal stress and improves the reliability of a semiconductor device, and to provide a stress relaxation sheet and its manufacturing method, and a semiconductor device, having the stress relaxation sheet and electronic equipment having the semiconductor device. SOLUTION: The stress relaxation structure, which has a wave-shaped insulating layer 4 that exists between a chip 5, on which a semiconductor device 6 is formed and a mounting substrate 7, has the above problem resolved by making the wiring 3 wave-shaped. In addition, the stress relaxed structure is formed, by forming an insulating layer 4 having a wavy shape that displaces in the thickness direction on a process substrate or a wafer, having a semiconductor element and forming wiring 3 having a wavy shape on the insulating layer. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种应力松弛结构及其在热应力下的应力松弛效果优异的形成方法，提高半导体装置的可靠性，提供应力松弛片及其制造方法，具有应力松弛片的半导体器件和具有半导体器件的电子设备。解决方案：在其上形成有半导体器件6的芯片5和安装基板7之间存在波形绝缘层4的应力松弛结构通过使布线3解决了上述问题波浪形。此外，通过在具有半导体元件的工艺衬底或晶片上形成具有在厚度方向上移位的波浪形状的绝缘层4，并且在绝缘层上形成具有波状的布线3，形成应力松弛结构。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2004179647A Wiring board, semiconductor package, and method for producing base insulating film and wiring board 有权
公开(公告)号：JP2004179647A
公开(公告)日：2004-06-24
申请号：JP2003382418
申请日：2003-11-12
申请人： Nec Corp , 日本電気株式会社
发明人： ORITO NAONORI , HONDA KOICHI , HO KEIICHIRO , MURAI HIDEYA , KIKUCHI KATSU , BABA KAZUHIRO
IPC分类号： H05K3/46 , H01L21/60 , H01L23/12
CPC分类号： H01L2224/16 , H01L2924/01046 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011
摘要： PROBLEM TO BE SOLVED: To provide a wiring board, in which various devices such as semiconductor device is mounted densely, a high-speed interconnection and dense fine-wiring are easily formed, and reliability is high; a semiconductor package using the wiring board; and to provide a method for producing the wiring board. SOLUTION: A base insulating film 7 is provided on a circuit board 13. In the base insulating film 7, it is set so that the thickness is 3 to 100 μm, breakdown strength is 80 MPa or larger at 23°C, and the elasticity modulus is 2.3 GPa or larger at 150°C. Assuming that the breakdown strength is a (MPa) at -65°C, and the breakdown strength is b (MPa) at 150°C, the ratio: a/b is set to 2.5 or smaller. Assuming that the elasticity modulus is c (GPa) at -65°C, and the elasticity modulus is d (GPa) at 150°C, the breakdown strength a, b and the elasticity modulus c, d satisfy the formula. COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2012033974A Wiring board and semiconductor package 有权
标题翻译：接线板和半导体封装
公开(公告)号：JP2012033974A
公开(公告)日：2012-02-16
申请号：JP2011248228
申请日：2011-11-14
申请人： Nec Corp , Renesas Electronics Corp , ルネサスエレクトロニクス株式会社 , 日本電気株式会社
发明人： YAMAMICHI SHINTARO , KIKUCHI KATSU , MURAI HIDEYA , FUNAYA TAKUO , MAEDA TAKEHIKO , OGAWA KENTA , TSUKANO JUN , HONDA HIROKAZU
IPC分类号： H01L23/12
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/6835 , H01L23/49811 , H01L23/49822 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/16235 , H01L2224/32057 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/83385 , H01L2224/92125 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/15183 , H01L2924/15311 , H01L2924/1532 , H01L2924/30107 , H01L2924/3011 , H01L2924/351 , H05K3/0055 , H05K3/20 , H05K3/421 , H05K3/4644 , H05K2201/09563 , H05K2201/09863 , H05K2203/0796 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a wiring board and a semiconductor package that can effectively cope with an increase in number of terminals due to high integration, acceleration or multiple functions of semiconductor devices as well as with a narrowing pitch of intervals between the terminals, and are excellent in reliability.SOLUTION: In the wiring board 13 in which a lower-layer wiring composed of a wiring body 6 and an etching barrier layer 5 is formed in a concavity 7a formed on one surface of a substrate insulator film 7, an upper-layer wiring 11 is formed on the other surface of the substrate insulator film 7, and the wiring body 6 of the lower-layer wiring and the upper-layer wiring 11 are formed on the substrate insulator film 7 and are mutually connected via a via hole 10, the via hole 10 is bellows-shaped.
摘要翻译：要解决的问题：提供一种布线板和半导体封装，其可以有效地应对由于半导体器件的高集成度，加速度或多种功能而导致的端子数量的增加以及间隔的间距变窄终端，可靠性好。解决方案：在形成在基板绝缘膜7的一个表面上的凹部7a中形成由布线体6和蚀刻阻挡层5构成的下层布线的布线基板13中，上层布线11形成在基板绝缘膜7的另一个表面上，下层布线和上层布线11的布线体6形成在基板绝缘膜7上，并且经由通孔10相互连接通孔10是波纹管状的。版权所有（C）2012，JPO＆INPIT

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