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1. 发明专利

JP5446132B2 Production method of planting for the pin and the pin with a printed wiring board 有权
公开(公告)号：JP5446132B2
公开(公告)日：2014-03-19
申请号：JP2008142244
申请日：2008-05-30
申请人：株式会社トッパンNecサーキットソリューションズ
发明人：将人小田
IPC分类号： H01L23/12 , H01L23/50
CPC分类号： H01L2224/16225 , H01L2924/15174 , H01L2924/15312

2. 发明专利

JP5272503B2 Erected for the pin and the pin with a printed wiring board 有权
公开(公告)号：JP5272503B2
公开(公告)日：2013-08-28
申请号：JP2008120996
申请日：2008-05-07
申请人：株式会社トッパンNecサーキットソリューションズ
发明人：利幸島
IPC分类号： H01L23/12 , H01L23/50
摘要： PROBLEM TO BE SOLVED: To provide a printed wiring board with a pin which prevents solder from excessively spreading over a rodlike part of a setting pin of the printed wiring board with the pin, and rigidly supports a nail head by a solder fillet. SOLUTION: On the printed wiring board 100 with the pin, a leading joint surface 1c of the nail head 1b of the setting pin is soldered to an external electrode 2 of the board 100. A groove 1e is formed on a rod placement surface 1d of the nail head 1b where the rodlike part 1a of the setting pin is placed. An inlet 1g of the groove is provided on a sidewall surface of the nail head 1b between the surface 1d and the joint surface 1c. An end of the solder fillet 7 in contact with the leading joint surface 1c is pulled up to the inlet 1g of the groove and solder is filled in the groove 1e. The solder in the groove 1e and the solder on the joint surface 1c enclose the nail head 1b for supporting. COPYRIGHT: (C)2010,JPO&INPIT

3. 发明专利

JP2013077763A Printed wiring board 审中-公开
标题翻译：印刷线路板
公开(公告)号：JP2013077763A
公开(公告)日：2013-04-25
申请号：JP2011217850
申请日：2011-09-30
申请人： Toppan Printing Co Ltd , 凸版印刷株式会社 , Nec Toppan Circuit Solutions Inc , 株式会社トッパンNecサーキットソリューションズ
发明人： OZAWA TATSURO , GOCHO SATOSHI , KAMATA MITSUAKI , AMEMIYA HIROYASU , KATO KATSUMUNE
IPC分类号： H05K3/46 , H05K1/02
摘要： PROBLEM TO BE SOLVED: To provide a printed wiring board having high reliability in prevention of forgery.SOLUTION: The printed wiring board according to the present invention includes: first and second insulating layers facing each other; a first conductor pattern interposed between the first and second insulating layers; and an insulating printed layer which is interposed between the first and second insulating layers, contains a phosphor for absorbing light having a first wavelength to emit light of a second wavelength different from the first wavelength, and is at least partially positioned between the second insulating layer and the first conductor pattern.
摘要翻译：要解决的问题：提供一种在防止伪造方面具有高可靠性的印刷线路板。解决方案：根据本发明的印刷电路板包括：彼此面对的第一和第二绝缘层; 插入在第一和第二绝缘层之间的第一导体图案; 并且介于所述第一绝缘层和所述第二绝缘层之间的绝缘印刷层包含用于吸收具有第一波长的光以发射不同于所述第一波长的第二波长的光的荧光体，并且至少部分地位于所述第二绝缘层和第一导体图案。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP5125242B2 Mounting structure of the semiconductor element, the printed circuit board and a method of manufacturing the same 有权
公开(公告)号：JP5125242B2
公开(公告)日：2013-01-23
申请号：JP2007157168
申请日：2007-06-14
申请人：株式会社トッパンNecサーキットソリューションズ
发明人：利幸島
IPC分类号： H01L23/12 , H01L23/36 , H01L23/473
CPC分类号： H01L2924/0002 , H01L2924/00

5. 发明专利

JP4983113B2 Wiring board and a method of manufacturing the same 有权
标题翻译：空值
公开(公告)号：JP4983113B2
公开(公告)日：2012-07-25
申请号：JP2006178142
申请日：2006-06-28
申请人：株式会社トッパンNecサーキットソリューションズ
发明人：博文中村 , 卓石岡
IPC分类号： H05K3/46 , H01L23/12
CPC分类号： H01L24/97 , H01L2224/04105 , H01L2224/18 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2224/83
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate with a built-in electron device that has high reliability in electrical connection of vias connected to the electron device in the wiring substrate with a built-in electron device, and to provide its manufacturing method. SOLUTION: A thermal expansion coefficient in a first region 11 is lower than that in a second region 12 other than the first region 11 in an insulating layer contacting with at least one face of the electron device 2. It is preferable that the insulating layer is a prepreg, and a reinforcement-material density in the first region 11 is higher than that of in the second region 12. By this, it is possible to improve reliability in connection of the vias while reducing a thermal-expansion-coefficient difference between the electron device 2 and the first region 11. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有内置电子器件的布线基板，其具有与内置电子器件连接到布线基板中的电子器件的通孔的电连接的高可靠性，并且提供其制造方法。解决方案：在与电子器件2的至少一个表面接触的绝缘层中，第一区域11中的热膨胀系数低于除第一区域11之外的第二区域12中的热膨胀系数。优选地，绝缘层是预浸料坯，并且第一区域11中的增强材料密度高于第二区域12中的增强材料密度。由此，可以提高通孔连接的可靠性，同时降低热膨胀系数电子设备2和第一区域11之间的差异。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP4244414B2 A method for manufacturing a multilayer printed wiring board 有权
公开(公告)号：JP4244414B2
公开(公告)日：2009-03-25
申请号：JP29365998
申请日：1998-10-15
申请人：株式会社トッパンNecサーキットソリューションズ
发明人：勝宗加藤 , 秀樹森 , 隆一横内 , 紘一石塚 , 龍雄鈴木
IPC分类号： B23K26/00 , H05K3/46 , B23K26/38 , H05K3/00 , H05K3/42
摘要： PROBLEM TO BE SOLVED: To actualize high-density wiring which has high electric reliability by eliminating a defect in plating and the peeling of a land part. SOLUTION: This multilayer printed wiring board has an insulating substrate 11, a lower wiring layer 12 formed partially on the insulating substrate, an insulating layer 14a which is formed on the insulating substrate and lower wiring layer, an upper wiring layer 18 which is formed partially on the insulating layer, and a via hole 31 which is formed in the internal wall of the insulating layer between the upper and lower wiring layers and electrically connects both the wiring layers. The diameter ϕ4 of the hole of the upper wiring layer connected to the via hole is larger than the diameter ϕ1 on the surface of the insulating layer of the via hole.

7. 发明专利

JP4117390B2 Method for producing a cavity-multilayer printed circuit board 有权
公开(公告)号：JP4117390B2
公开(公告)日：2008-07-16
申请号：JP2003129332
申请日：2003-05-07
申请人：株式会社トッパンNecサーキットソリューションズ
发明人：修太長根
IPC分类号： H05K3/00 , H05K3/46
CPC分类号： H01L2924/15153 , H01L2924/1517

8. 发明专利

JP4103502B2 Multilayer wiring board and a method of manufacturing the same 有权
公开(公告)号：JP4103502B2
公开(公告)日：2008-06-18
申请号：JP2002249452
申请日：2002-08-28
申请人：株式会社トッパンNecサーキットソリューションズ
发明人：清貴広田
IPC分类号： H05K3/46

9. 发明专利

JP2008091957A Soldering method 有权
标题翻译：焊接方法
公开(公告)号：JP2008091957A
公开(公告)日：2008-04-17
申请号：JP2007335795
申请日：2007-12-27
申请人： Arakawa Chem Ind Co Ltd , Maruya Seisakusho:Kk , Nec Infrontia Corp , Nec Toppan Circuit Solutions Inc , Necインフロンティア株式会社 , Nihon Dennetsu Keiki Co Ltd , Sorudaa Kooto Kk , ソルダーコート株式会社 , 日本電熱計器株式会社 , 株式会社トッパンNecサーキットソリューションズ , 株式会社マルヤ製作所 , 荒川化学工業株式会社
发明人： TANABE KAZUHIKO , TERADA HIROAKI , SUGIURA MASAHIRO , MIZUTANI TETSUJI , IMAMURA KEIICHIRO , TANAKA TAKASHI
IPC分类号： H05K3/34
摘要： PROBLEM TO BE SOLVED: To achieve solder-packaging of a printed circuit board with the excellent soldering quality and reliability by certainly preventing land lifting at the time of using a lead-free solder. SOLUTION: The soldering method for soldering a printed circuit board having portions to be soldered on both sides, comprising the steps of reflow soldering of electronic parts with a lead-free solder made of at least tin, silver and copper on one surface of the printed circuit board, and flow soldering with a tin-9 zinc solder with the part to be soldered, formed on the other surface of the printed circuit board controlled in a temperature range of 220°C to 230°C and the temperature of the soldered part by the reflow soldering maintained at 178°C or lower. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过在使用无铅焊料时肯定防止土地抬升，实现出色的焊接质量和可靠性来实现印刷电路板的焊接包装。解决方案：用于焊接具有要焊接在两面上的部分的印刷电路板的焊接方法，包括以下步骤：在一个表面上用至少锡，银和铜制成的无铅焊料回流焊接电子部件的印刷电路板，并且用锡-9锌焊料与要焊接的部件进行流动焊接，形成在控制在220℃至230℃的温度范围内的印刷电路板的另一个表面上，并且温度通过回流焊接的焊接部件保持在178℃以下。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2007242879A Subunit substrate 审中-公开
标题翻译：子电子基板
公开(公告)号：JP2007242879A
公开(公告)日：2007-09-20
申请号：JP2006063001
申请日：2006-03-08
申请人： Nec Toppan Circuit Solutions Inc , 株式会社トッパンNecサーキットソリューションズ
发明人： KIKUCHI HIDEO , SHIMA TOSHIYUKI , KAMATA MITSUAKI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a subunit substrate effective to reduce a ground bounce generated by the resonance of an LC resonance circuit composed of parasitic capacitance and parasitic inductance.
SOLUTION: The subunit substrate 1 has a region where a sub substrate power supply layer 3 having a sub substrate power supply pattern 35 and a sub substrate ground layer 2 having a ground pattern 21 face each other via an insulating layer. For a sub-substrate power supply pattern with a size D half or more of the size of the subunit substrate the number n of sub-substrate power supply terminals connected to the sub-substrate power supply pattern is 2.9*h/t or more, where (h) is the height of the sub-substrate power supply terminal and (t) is an interval between the sub-substrate power supply pattern and the ground pattern or an overlapping area of the sub-substrate power supply pattern, and the ground pattern is 0.25 or less of the area of the subunit substrate and is 0.35*(n*t/h) or more.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种有效地减少由寄生电容和寄生电感组成的LC谐振电路的谐振产生的接地反弹的子单元基板。解决方案：子单元基板1具有通过绝缘层具有副基板电源图案35的副基板电源层3和具有接地图案21的副基板接地层2的区域。对于尺寸为子单元基板尺寸的半数以上的子基板电源图案，与子基板电源图案连接的子基板电源端子的数量n为2.9×h / t以上，其中（h）是子基板电源端子的高度，（t）是子基板电源图案和接地图案之间的间隔或者子基板电源图案的重叠区域，以及地面图案为亚基底物面积的0.25以下，为0.35 *（n * t / h）以上。版权所有（C）2007，JPO＆INPIT

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