专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH0879281A DIAGNOSTIC SYSTEM FOR BUS FAULT 失效
公开(公告)号：JPH0879281A
公开(公告)日：1996-03-22
申请号：JP20963494
申请日：1994-09-02
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SHINPO HIDEO , MORIYA HIROSHI , MASUDA ETSUO
IPC分类号： H04L12/40
摘要： PURPOSE: To provide a bus fault diagnostic system capable of quickening a fault diagnosis at the time of detecting bus communication abnormality, avoiding an erroneous processing accompanying the system changeover of normal equipment and reducing the operations of a maintenance person. CONSTITUTION: In this system composed of a '0' system bus 000 and a '1' system bus 100 for which the plural equipment including central processing units (CPUs) 010 and 110 are connected to one common bus, central controllers 010 and 110 are provided with a program for testing the normality of the internal circuits of the respective equipment, the program for testing the normality of a communication function from the CPUs 010 and 110 to the respective equipment through the buses, a diagnostic scenario and the program for interpreting and executing the diagnostic scenario. By executing the diagnostic scenario before cutting off any equipment from the system with the fact that the CPUs 010 and 110 detect abnormality in communication through the buses as a trigger, a faulty equipment is specified.

2. 发明专利

JP2000035897A DEVICE DETACHING SYSTEM 失效
公开(公告)号：JP2000035897A
公开(公告)日：2000-02-02
申请号：JP20202098
申请日：1998-07-16
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD , HITACHI LTD , NEC CORP , OKI ELECTRIC IND CO LTD
发明人： MASUDA ETSUO , SHINPO HIDEO , MURAKAMI TAKAO , HATAE KENICHIRO , HIRANO YUICHI , TAWARA TAMOTSU
IPC分类号： G06F11/20 , G06F13/00
摘要： PROBLEM TO BE SOLVED: To flexibly cope with the change of the number of devices and to securely detach them without a manual operation by installing a complete suppression-type detaching means by way of a maintenance bus and a restrictive communication possible-type detaching means by way of a system bus. SOLUTION: MPU 12 in CPU 10 sets a detaching command in a register in CNC 14 and starts it. Then, μP 15 receiving an interruption from CNC 14 reads the command which is set in CNC 14, checks normality and sets the detaching command in MBC 17. MBC 17 designates a device i20 in accordance with a prescribed protocol and sends the detaching command to the maintenance bus MB. Then, MBC 28 of the device i20 receiving the command sets DV/RV 31 in an electrically cut state via a detaching signal 32 and transmits an answer. The, μP 15 reads the answer from MBC 17 which receives the answer writes the answer against CNC 14 and makes an interruption for the termination of command execution on MPU 12 then, the detachment of the device completes.

3. 发明专利

JPH04252315A PROCESSOR RESETTING METHOD 失效
公开(公告)号：JPH04252315A
公开(公告)日：1992-09-08
申请号：JP2690291
申请日：1991-01-28
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MASUO KAZUYUKI , KOMATSUBARA TSUTOMU , SHINPO HIDEO
IPC分类号： G06F1/24 , G06F13/00 , H04M3/22 , H04Q3/545
摘要： PURPOSE:To apply a general-purpose microprocessor chip even to a processor of a switchboard, etc., that requires the high reliability processor by attaining the initialization to each operation mode of the processor with a simple means. CONSTITUTION:The factor of initialization is set to a reset status register RSR with an initialization request and a microprocessor muP is started. The mode definition date stored in a ROM is set to 8 relevant register group RSG. Then the muP reads the RSR and analyzes the factor of initialization. In regard of the general initialization, e.g. a resetting operation performed through an external switch, the normal initialization processing is carried out. In regard of the initialization proper to an operating mode, i.e., a reset state caused by a trouble, the trouble recovering method is decided based on the date on the operation mode. Then, an initialization routine is selected and carried out in response to each operation mode. The muP clears the RSR at the end of an initial routine and runs or halts a central processor unit CPU in response to the operation mode. Finally the muP halts itself.

4. 发明专利

JPH03204727A INTERRUPTION CONTROL CIRCUIT 失效
公开(公告)号：JPH03204727A
公开(公告)日：1991-09-06
申请号：JP47590
申请日：1990-01-08
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： AZUMA ISAO , KOBAYASHI MASAMITSU , SHINPO HIDEO
IPC分类号： G06F9/48 , G06F9/46
摘要： PURPOSE:To group interruption requiring signals by a small number of registers by using encoding registers for storing the information for encoding an interruption group number, respectively in accordance with the interruption request signal. CONSTITUTION:At the time of registering an interruption requiring signal, only encoding registers 110 - 119 corresponding to an interruption requiring origin to be registered become a writable state by each bit of data for indicating the interruption requiring origin and a write signal. An address converting circuit 150 converts address information for designating an interruption group to the information for the encoding registers 110 - 119. Subsequently, the encoding registers 110 - 119 which become a writable state store encoding information from the address converting circuit 150. At the time of inputting an interrupting signal, output selection parts 120 - 129, 130 - 135 select the encoding register 110 - 119 corresponding to this input signal, and output the encoding information stored in these encoding register as an interruption group number. In such a manner, the interruption requiring signal can be grouped by the small number of registers.

5. 发明专利

JPH11143817A INFORMATION PROCESSING SYSTEM, SYSTEM BUS TESTING METHOD AND STORAGE MEDIUM RECORDING ITS PROCESSING PROGRAM 失效
公开(公告)号：JPH11143817A
公开(公告)日：1999-05-28
申请号：JP31207697
申请日：1997-11-13
申请人： NIPPON TELEGRAPH & TELEPHONE , NEC CORP , FUJITSU LTD , OKI ELECTRIC IND CO LTD , HITACHI LTD
发明人： MASUDA ETSUO , SHINPO HIDEO , ISHIKAWA YASUHIRO , IKEDA KOJI , KOBAYASHI HIROSHI , HASHIMOTO HIROSHI
IPC分类号： G06F11/22 , G06F13/28
摘要： PROBLEM TO BE SOLVED: To efficiently execute the performance test of a system bus at an information processing system. SOLUTION: DMAC 8 provided in an input/output controller 4 is started from CPU(central processing unit) 1 and pseudo DMA transfer (DMA transfer without operating a subordinate input/output device) is executed between the controller 4 and a main memory 2 through the DMAC(direct memory access controlling circuit) 8 to give a load to a system bus by this pseudo DMA transfer to test durability and stability of the system bus in the configuration of the information processing system.

6. 发明专利

JPH043237A MAIN STORAGE DEVICE PROTECTING SYSTEM 失效
公开(公告)号：JPH043237A
公开(公告)日：1992-01-08
申请号：JP10460090
申请日：1990-04-20
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SHINPO HIDEO , KOMATSUBARA TSUTOMU , SHINTANI HIROSHI
IPC分类号： G06F12/16
摘要： PURPOSE:To prevent the deterioration of the performance of the system, and also, to secure the data until immediately before a fault is generated by providing a buffer memory for holding temporarily the data, and sending out an error informing signal from an error detecting circuit added to a central processing unit. CONSTITUTION:To a central processing unit 1, an error detecting circuit 2 for detecting an error of a control signal required for writing data outputted therefrom, an address for showing a store position of its data, and the data to a main storage device 3 is added. Also, between the central processing unit 1 and the main storage device 3, or in the main storage device 3, a buffer memory 4 for holding temporarily write data is provided, and moreover, an error informing signal line 6 for informing an error of output data detected by the error detecting circuit 2 to the buffer memory 4 is provided. The buffer memory 4 holds temporarily the data at the time of writing the data from the central processing unit 1, and rejects the held data, in the case an error notice is received from the error detecting circuit 2. In such a way, the perfor mance deterioration of the system is not caused, and also, the data until immedi ately before a fault is generated can be secured.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式