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1. 发明专利

JP2000035897A DEVICE DETACHING SYSTEM 失效
公开(公告)号：JP2000035897A
公开(公告)日：2000-02-02
申请号：JP20202098
申请日：1998-07-16
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD , HITACHI LTD , NEC CORP , OKI ELECTRIC IND CO LTD
发明人： MASUDA ETSUO , SHINPO HIDEO , MURAKAMI TAKAO , HATAE KENICHIRO , HIRANO YUICHI , TAWARA TAMOTSU
IPC分类号： G06F11/20 , G06F13/00
摘要： PROBLEM TO BE SOLVED: To flexibly cope with the change of the number of devices and to securely detach them without a manual operation by installing a complete suppression-type detaching means by way of a maintenance bus and a restrictive communication possible-type detaching means by way of a system bus. SOLUTION: MPU 12 in CPU 10 sets a detaching command in a register in CNC 14 and starts it. Then, μP 15 receiving an interruption from CNC 14 reads the command which is set in CNC 14, checks normality and sets the detaching command in MBC 17. MBC 17 designates a device i20 in accordance with a prescribed protocol and sends the detaching command to the maintenance bus MB. Then, MBC 28 of the device i20 receiving the command sets DV/RV 31 in an electrically cut state via a detaching signal 32 and transmits an answer. The, μP 15 reads the answer from MBC 17 which receives the answer writes the answer against CNC 14 and makes an interruption for the termination of command execution on MPU 12 then, the detachment of the device completes.

2. 发明专利

JPH1165879A BUS INTERFACE TESTING METHOD AND STORAGE MEDIUM RECORDING PROCESSING PROGRAM THEREFOR 失效
公开(公告)号：JPH1165879A
公开(公告)日：1999-03-09
申请号：JP22245897
申请日：1997-08-19
申请人： NIPPON TELEGRAPH & TELEPHONE , NEC CORP , HITACHI LTD , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： MASUDA ETSUO , SHIMIZU KOICHI , MURAKAMI TAKAO , NISHII HIROSHI , HIRANO YUICHI , TAWARA TAMOTSU
IPC分类号： G06F3/00 , G06F11/22
摘要： PROBLEM TO BE SOLVED: To provide a bus interface testing method and a storage medium recording processing program therefor by which the fault detection accuracy of an interface test can be improved. SOLUTION: When the number of signal lines as a bus interface test object is an odd number, 'write' (101) and 'read' (103) used for a conventional test are performed while switching respective opposite patterns like all '1' and all '0', for example, (100 and 200) and a parity check is performed (102 and 104) so that the one-bit stack fault of driver and receiver elements at a bus interface part can be detected. When the number of signal lines as the test object is an even number, a 3rd pattern to be the opposite party value to two other patterns is used (300). Further, the pattern when written and the pattern when read are collated in the respective patterns (105 and 106) and failure except for a parity error is detected as well.

3. 发明专利

JPH08297633A BUS ARBITER AND BUS ARBITRATING SYSTEM USING SAME 失效
公开(公告)号：JPH08297633A
公开(公告)日：1996-11-12
申请号：JP10326495
申请日：1995-04-27
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： NIWA YUJI , MURATANI MASATO , ASAI MASAO , MURAKAMI TAKAO , ISHIKAWA EIJI
IPC分类号： G06F13/368
摘要： PURPOSE: To constitute a bus arbitrating system with which common bus resources can be effectively utilized. CONSTITUTION: Concerning a bus arbiter of a system mutually connecting a processor side bus 1 and a non-processor side bus 3 through a bus repeater that can bisect the bus, this bus arbiter is provided with a first arbitration part for arbitrating the bus right request signal of the bus 1 and a second arbitration part for arbitrating the bus right request signal of the bus 3 and the first and second arbitration parts respectively independently arbitrate the respective bus right request signals of buses 1 and 3. Preferably, the bus repeater recognizes the direction of bus access according to a bus access signal generated by a bus master, when repetition is required, a repetition request signal for acquiring the bus right of the bus 1 or 3 is generated, and the first or second arbitration part arbitrates the bus right request signal of the bus 1 or 3 and the repetition request signal to the bus 1 or 3 together.

4. 发明专利

JPH11282781A Communication device 失效
标题翻译：通信设备
公开(公告)号：JPH11282781A
公开(公告)日：1999-10-15
申请号：JP8131798
申请日：1998-03-27
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd , 富士通株式会社 , 日本電信電話株式会社 , 沖電気工業株式会社
发明人： KITAMURA TATSUHIKO , WADA SUKEMICHI , KOGURE TAKUYA , ITO ARATA , MURAKAMI TAKAO
IPC分类号： G06F13/14 , G06F13/00
摘要： PROBLEM TO BE SOLVED: To unnecessitate the reset of inherent device data at the time of exchanging device control packages.
SOLUTION: A device control package 10a for controlling this communication device is mounted on a back panel 14 by using a specified connector 12. The device control package has an interface to be connected to a LAN 16. The device control package is equipped with a work station 22 outside and input of data by way of this interface can be performed from the work station. The device control package is equipped with an in-package control part 20 mounting a CPU. The in-package control part controls a sub board 24a as well as the mounted whole device control package. The sub board is connected to the back panel by using a specified connector 26. The sub board and the device control package are connected by the back panel with a signal wiring 28. The sub board is equipped with a storage device 18 where inherent device data such as an IP address are recorded.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：在更换设备控制包时，不必要重置固有的设备数据。解决方案：用于控制该通信设备的设备控制包10a通过使用指定的连接器12安装在后面板14上。设备控制包具有要连接到LAN 16的接口。设备控制包装配有工作站外22，通过该接口输入数据可以从工作站进行。设备控制包装有安装CPU的包装内控制部件20。包装内控制部分控制子板24a以及安装的整个装置控制包装。子板通过使用指定的连接器26连接到后面板。子板和设备控制封装通过背板与信号布线28连接。子板配备有存储装置18，其中固有的装置数据如IP地址被记录。

5. 发明专利

JPS5990141A INFORMATION PROCESSING SYSTEM OF VARIABLE STRUCTURE TYPE 失效
公开(公告)号：JPS5990141A
公开(公告)日：1984-05-24
申请号：JP19905482
申请日：1982-11-15
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MURAKAMI TAKAO , TOKUYAMA GOROU , TAKAHIRA SATOSHI
IPC分类号： G06F7/00 , G06F7/38
摘要： PURPOSE:To replace the repetition of plural same circuits with a single circuit and to simplify a circuit constitution by performing many equal parallel operations and setting dynamically an indication for an optional digit number within a limited number of feedback loop stages and an optional combination of digit lengths. CONSTITUTION:A circuit A which performs many parallel operations at a time delivers an output to an output terminal O and at the same time feeds a part of the output to a selection circuit S. A delay loop circuit R supplies the gate control information and has the logic stage number corresponding to the number of simultaneous multiplex processes of the circuit A. The circuit S selects the information given from a data input terminal I and the feedback information given from the circuit A based on the control information given from the circuit R and supplies them to the circuit A. The gate control information to decide the selection of the data from an input I or the circuit A is set previously from an input B to the circuit R. Then the circuit S supplies only the data fed from I to the circuit A to perform the multiplex arithmetic processing, otherwise the feedback information fed from the circuit A is supplied. Thus it is possible to set an optional digit number and to have an optional combination of digit numbers.

6. 发明专利

JPS60215248A INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPS60215248A
公开(公告)日：1985-10-28
申请号：JP4671984
申请日：1984-03-12
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TOKUYAMA GOROU , MURAKAMI TAKAO
IPC分类号： G06F7/00 , G06F9/44 , G06F15/82
摘要： PURPOSE:To omit the function parts for instruction words and instruction cells and to improve the information processing capacity, by providing arithmetic circuits according to the types of operations and allocating a memory area to each arithmetic circuit. CONSTITUTION:Arithmetic circuits 1-1-1-16 consist of adders A0 and A1, subtractors S0 and S1, multipliers MU0-MU3, dividers DIV0 and DIV1, a circulating right shifter SRC, a plus jumper JP, an AND, an OR, an X AND/NOT Y, a loop LOOP, etc. Memories 2-1-2-16 corresponding to said arithmetic circuits consist of words #0-#3. Each of these words is divided into fields of a left operand L, a right operand R, the numerical value V, a transfer receiver TR, etc. A distribution circuit 5 includes a register part 6 containing 16 registers in all in response to each arithmetic circuit and a scan transfer part 7 which monitors the part 6 and transfers information to a designated memory. An auxiliary memory 8 is used to store the information on the transfer receiver in case plural transfer receivers of information exist and it is impossible for the TR part of a memory to designate these receivers.

7. 发明专利

JPS5660946A CHARACTER PRINT OR DISPLAY SYSTEM AVAILABLE FOR BOTH HORIZONTAL WRITING AND VERTICAL WRITING 失效
公开(公告)号：JPS5660946A
公开(公告)日：1981-05-26
申请号：JP13706979
申请日：1979-10-25
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MURAKAMI TAKAO , KANBARA SHINICHI , KATSUKAWA TAKASHI , TOGAWA MAKOTO
IPC分类号： G06F3/12 , B41J5/30 , G06K15/00 , G09G5/24
摘要： PURPOSE:To attain the distribution of data, by facilitating output processing and to increase the operation speed of the device by making it possible to represent the same data inputted from a data input medium in the natural form of both horizontal writing and vertical writing. CONSTITUTION:Storage address table 6 for horizontal-writing character font pattern contains addresses in character generator 3 storing horizontal writing character font patterns. On the other hand, vertical-writing character font pattern storage address table 7 contains addresses in device 3 stored with vertical-writing character font patterns. Under the vertical-writing or horizontal writing command from data input medium 1, the address of the font pattern of a specific character in storage address table 5 is converted to that of table 6 or 7 in a natural form. Consequently, the distribution of data can be obtained, the output processing is facilitated and the operation speed of the device can be improved.

8. 发明专利

JP2004178374A Multiprocessor system 有权
公开(公告)号：JP2004178374A
公开(公告)日：2004-06-24
申请号：JP2002345371
申请日：2002-11-28
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MATSUURA HIROKAZU , MURAKAMI TAKAO , UNO KAZUYA
IPC分类号： G06F9/46 , G06F9/52 , G06F12/00 , G06F12/06 , G06F12/08 , G06F15/167 , G06F15/177
CPC分类号： G06F9/52 , G06F12/0806
摘要： PROBLEM TO BE SOLVED: To reduce frequency of access to a common memory, even if there are competitions for access to the common memory from each processor.
SOLUTION: In a multiprocessor system, a number of data areas which stores data in the common memory and a control information area which stores control information indicating an in-use state for each data area. Each processor is provided with a memory unit, equivalent to the common memory and an access control section. The access control section of a processor having no access right monitors data flowing on a common bus and its address, fetches and stores data writing to the common memory and data reading from the common memory in the memory unit of its own processor, and holds the content identical to the common memory.
COPYRIGHT: (C)2004,JPO

9. 发明专利

JPH05134983A SERIAL/PARALLEL CONVERSION TRANSFER SYSTEM 失效
公开(公告)号：JPH05134983A
公开(公告)日：1993-06-01
申请号：JP13884191
申请日：1991-06-11
申请人： FUJITSU LTD
发明人： MURAKAMI TAKAO
IPC分类号： G06F13/38
摘要： PURPOSE:To shorten a time required for bus arbitration by performing start-up transfer and response transfer for it by one time of transfer request between a system bus intersection control part and a serial bus intersection control part. CONSTITUTION:When a start-up transfer request signal is outputted from a serial bus intersection control part 20 to a system bus intersection control part 10, the system bus intersection control part 10 returns a transfer permission signal to the serial bus intersection control part 20, and transfers the content of a reception buffet 21 from the data delivery part 22 of the serial bus intersection control part 20 to the system bus intersection control part 10. The serial bus intersection control part, when receiving a data reception completion signal from the system bus intersection control part 10. receives data delivered from the system bus intersection control part 10 by a data reception part 23, and supplies it to a serial bus as serial data. Thereby, it is possible to perform the start-up transfer and the response transfer for it in one time of transfer request, and to reduce a time required for the bus arbitration.

10. 发明专利

JPS61109348A Bus termination system 失效
标题翻译：总线终端系统
公开(公告)号：JPS61109348A
公开(公告)日：1986-05-27
申请号：JP23094284
申请日：1984-11-01
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp
发明人： MURAKAMI TAKAO , KITANO HIROSHI
IPC分类号： H04Q3/545
摘要： PURPOSE: To simplify the extension work by connecting a bus connecting an input/output device in an extension device to a controller independently of a bus connecting input/output devices in a basic device so as to eliminate the need for the connection change of a termination resistor of the bus in extending the input/output device.
CONSTITUTION: A driver DV2 transmitting signal to a bus B2 connected to the input/output device IO2 of the extension device ED is provided to a controller CTL' in the basic device BD in addition to a driver DV1 transmitting a signal to a bus B1 connected to the input/output device IO1 in the device BD. The remote ends of the buses B1, B2 are terminated by termination resistors R1, R2. Then the change of the termination resistor R1 in the device BD1 is not required in extending the input/output device ID2 in the extension device ED so as to simplify the extension work.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了简化扩展工作，通过将连接扩展设备中的输入/输出设备的总线连接到控制器，无需连接基本设备中的输入/输出设备的总线，从而消除对终端的连接更改的需要总线的电阻在扩展输入/输出设备。构成：除了连接到连接到总线B1的信号的驱动器DV1之外，向连接到扩展装置ED的输入/输出装置IO2的总线B2发送信号的驱动器DV2提供给基本装置BD中的控制器CTL' 到设备BD中的输入/输出设备IO1。总线B1，B2的远端由端接电阻R1，R2端接。然后，在扩展设备ED中的输入/输出设备ID2的扩展中，不需要在设备BD1中改变终端电阻器R1，从而简化扩展工作。

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