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1. 发明专利

JPH08331189A CLOCK PHASE SYNCHRONIZATION CIRCUIT 失效
公开(公告)号：JPH08331189A
公开(公告)日：1996-12-13
申请号：JP13070695
申请日：1995-05-29
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SEKI KAZUHIKO , KUBOTA SHUJI , KATO SHUZO
IPC分类号： H04L27/22 , H04L7/00 , H04L25/40
摘要： PURPOSE: To synchronize a clock signal of a receiver side with a frequency of a signal froth a transmitter side at a high speed without forming a phase locked loop by providing a counter circuit that is preset by a change point detection pulse or a carryout signal of a clock circuit itself, increments its count synchronously with an output signal from a local frequency oscillation circuit and provides part of a count digit represented by a binary number as an output of a clock signal with a frequency higher than the frequency of the data clock signal to the synchronization circuit. CONSTITUTION: A receiver of a digital signal is provided with a local frequency oscillating circuit 106 not phase-locked with a local oscillating frequency of a transmitter. A clock recovery circuit 102 recovers a data clock signal from a reception signal. A differentiation circuit 103 detects a change point of a recovered clock signal to generate a change point detection pulse. A counter circuit 104 is preset by the change point detection pulse or the carryout signal from the counter circuit 104 itself and counts up its count synchronously with a signal outputted from the local frequency oscillating circuit 106 and provides an output of part of the count digits represented in a binary number as a clock signal with a frequency higher than that of the data clock signal.

2. 发明专利

JP2530965B2 失效
公开(公告)号：JP2530965B2
公开(公告)日：1996-09-04
申请号：JP5097392
申请日：1992-03-09
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KOBAYASHI SEI , SEKI KAZUHIKO , MORIKURA MASAHIRO , KATO SHUZO
IPC分类号： H04L27/227 , H04L27/22

3. 发明专利

JPH06188730A FREQUENCY SYNTHESIZER 失效
公开(公告)号：JPH06188730A
公开(公告)日：1994-07-08
申请号：JP34063292
申请日：1992-12-21
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SEKI KAZUHIKO , KATO SHUZO
IPC分类号： H03L7/087 , H03L7/18
摘要： PURPOSE:To obtain a frequency synthesizer which stably operates without requiring a temperature compensating circuit by placing a frequency synchronizing loop in operation so as to match the oscillation frequency of VCO with a specified frequency after switching without reference to f-V characteristics of VCO. CONSTITUTION:A frequency detector 10 detects an output frequency fvco fed back from the VCO in a phase-locked loop PLL at the time of frequency switching. The difference between the detected value and the specified frequency after the switching is outputted. An integrator 16 cumulatively adds the difference that the detector 10 outputs. Further, a zero detector 17 checks the difference that the detector 10 outputs and a D-A converter 19 converts the output of the integrator 16 from digital to analog and then supplies the result to the VCO. The output frequency fvco of the VCO is fed back to the detector 10 and the zero detector 17 repeats the operation of the detector 10, integrator 16, and D-A converter 19 until the fed-back difference signal reaches 0. Consequently, the frequency synthesizer which stably operates without requiring any temperature compensating circuit is obtained.

4. 发明专利

JPH01200844A SYSTEM FOR CONVERTING FREQUENCY 失效
公开(公告)号：JPH01200844A
公开(公告)日：1989-08-14
申请号：JP2518888
申请日：1988-02-05
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KAZAMA HIROSHI , SEKI KAZUHIKO , SHOMURA TATSURO , FUNEKAWA KIMITOSHI
IPC分类号： H04J13/00 , H04B1/7136 , H04L5/26
摘要： PURPOSE:To reduce the number of frequency oscillating circuits to the number of hopping carriers or below and to decrease a hardware quantity by providing plural variable frequency oscillating circuits to be set at arbitrary frequencies, a frequency control circuit, etc. CONSTITUTION:For each of variable frequency oscillating circuits 11-14, an output frequency is arbitrarily set by the control signal of a frequency control circuit 17, and the signals of output frequencies f1-f4 of the circuits 11-14 are inputted to an oscillator switching circuit 15. Next, the circuit 15 selects one of input signals, and the signal is inputted to a frequency converting circuit 16. The frequency changes of the circuits 11-14 are executed while the circuits 11-14 are not selected by the circuit 15, and the frequency setting and the selection switching of the circuit 15 are controlled in a time slot unit. Thus, since an arbitrary frequency can be outputted and the number of circuits 11-14 can be reduced to the number of hopping carriers or below, the hardware quantity can be decreased.

5. 发明专利

JPH0738530A ORTHOGONAL PHASE MODULATION CIRCUIT 失效
公开(公告)号：JPH0738530A
公开(公告)日：1995-02-07
申请号：JP18419393
申请日：1993-07-26
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SEKI KAZUHIKO , SAKATA TORU , KATO SHUZO
IPC分类号： H03C3/00 , H04B1/713 , H04J3/00 , H04L27/20 , H04J13/06
摘要： PURPOSE:To perform the switching of a carrier frequency at high speed by partially taking charge of the switching of the carrier frequency with a frequency convert phase modulation part composed of a digital circuit for performing phase modulation and a synthesizer. CONSTITUTION:A frequency phase modulation part 110 composed of the digital circuit generates a modulated output signal for which frequency conversion and orthogonal phase modulation are performed by orthogonal sine waves at plural frequencies instructed to a base band signal 191 by the low-order digit of a carrier frequency instructing signal 192. This phase-modulated output signal is mixed with the output carrier signal of a synthesizer 107 for outputting a carrier signal based on the high-order digit of the carrier frequency instructing signal 192, and a phase-modulated ratio frequency signal is generated. In this case, the frequency convert phase modulation part 110 performs the frequency conversion and the orthogonal phase modulation by generating the orthogonal sine waves at the small number of low frequencies instructed by the low-order digit of the carrier frequency instructing signal 192 without necessity for performing the modulation corresponding to all the channels.

6. 发明专利

JPH06252783A SILENCE DETECTION CIRCUIT 失效
公开(公告)号：JPH06252783A
公开(公告)日：1994-09-09
申请号：JP3344093
申请日：1993-02-23
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： DOBASHI AKIRA , NAKAMURA OSAMU , SEKI KAZUHIKO , KUBOTA SHUJI , KATO SHUZO
IPC分类号： H04B1/04
摘要： PURPOSE:To provide a silence detection circuit able to accurately detect the presence of an input voice signal regardless of the quantity of an average level of the input voice signal. CONSTITUTION:The detection circuit is provided with an automatic gain control circuit 6' in which a gain of a variable gain amplifier 5 is controlled so that the input voice signal after amplification reaches a predetermined level when a silence discrimination circuit 4 discriminates the presence of an input voice signal and the gain of the variable gain amplifier 5 is controlled to have a value discriminated to be presence of the input voice just before when the absence of the input voice signal is discriminated, then the input voice signal is amplified up to a predetermined level independently of the quantity of the average level and input noises at silence is not amplified.

7. 发明专利

JPH06204961A SYNCHRONIZING WORD DETECTING CIRCUIT 失效
公开(公告)号：JPH06204961A
公开(公告)日：1994-07-22
申请号：JP185793
申请日：1993-01-08
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SEKI KAZUHIKO , KATO SHUZO
IPC分类号： H04B7/26 , H04J3/00 , H04J3/06 , H04L7/02 , H04L7/04 , H04L7/10
摘要： PURPOSE:To ensure the stable synchronization control by integrating the reception levels at each time slot position to decide a time slot position where the largest integration value is shown and then setting a synchronizing word detecting time window corresponding to the decided time slot position. CONSTITUTION:The reception level (b) of the received signal (a) is detected at either one of time slot positions within a measurement frame and then integrated by the corresponding one of integrators 211-218. Thus the reception levels are averaged at each time slot position, and a largest value deciding circuit 22 can accurately detect the time slot position t2 that includes the burst signal received from the base station having the best receiving conditions. A timing circuit 23 produces a synchronizing word detecting time window (e) based on the position t2 and gives the window (e) to a correlation detector 14. Thus the detector 14 can improve the detecting probability of a desired synchronizing word by the window (e) and also can improve the probability of the burst signal received from the base station of the best receiving conditions for a receiver.

8. 发明专利

JPH0974387A RADIO TRANSMITTER AND RADIO RECEIVER 失效
公开(公告)号：JPH0974387A
公开(公告)日：1997-03-18
申请号：JP22885795
申请日：1995-09-06
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SEKI KAZUHIKO , KUBOTA SHUJI
IPC分类号： H04B14/06
摘要： PROBLEM TO BE SOLVED: To transmit other medium data without interrupting sound transmission by time division multiplexing error correction encoding codes with the medium data in a multiplex circuit and radio transmitting them. SOLUTION: In this radio transmitter, ADPCM(adaptive differential pulse code modulation) codes 112 are inputted to a Huffman encoder as a compression encoder and converted Huffman codes are turned to BCH(Base-change- Hocquenghem) codes by executing encoding for error correction by a BCH encoder as an error correction encoder 103, tentatively stored in a butter, sent out following flag signals, multiplexed with the other medium data 115 by the multiplex circuit 104 further and turned to transmission signals. At the time, the bit number of the Huffman codes is counted in a coefficient device, an error correction code for a corresponding block inside the butter is read for each encoding block in the BCH encoder, the flag signal is attached to the head and a multiplex control circuit controls the butter and the multiplex circuit 104 so as to multiplex sound to the other medium data 115 for each BCH code length.

9. 发明专利

JPH0936830A METHOD FOR GENERATING SPREAD SPECTRUM SIGNAL, TRANSMITTER AND DEMODULATOR 失效
公开(公告)号：JPH0936830A
公开(公告)日：1997-02-07
申请号：JP18540595
申请日：1995-07-21
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MIZOGUCHI MASATO , SEKI KAZUHIKO
IPC分类号： H04J13/00 , H04B1/692 , H04J13/02
摘要： PROBLEM TO BE SOLVED: To demodulate an FH/DS spectrum in the circuit of a simple constitution without using an FH synchronizing control circuit and a frequency hopping synthesizer, in a spread spectrum communication in which communication is more stably performed in a propagation path where phasing and interference exist. SOLUTION: In the method for generating a spread spectrum signal in which a spreading code defining one period that the symbol period of transmission data is divided into plural ones as one chip is generated, a direct spread spectrum signal is generated by directly spreading the spectrum of a transmission code by the spreading code and a transmission signal is generated by performing a frequency conversion into plural carrier frequencies for the direct spread spectrum signal, the one-chip period of the generated spreading code is divided into N (N is an integer >=2), the carrier frequency is switched so that each sub-chip may be outputted on the N carrier frequencies one time within the one-chip period and the transmission signal is generated.

10. 发明专利

JPH07219773A SYSTEM AND CIRCUIT FOR MEMORY DATA ARITHMETIC 失效
公开(公告)号：JPH07219773A
公开(公告)日：1995-08-18
申请号：JP1427794
申请日：1994-02-08
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SEKI KAZUHIKO , KATO SHUZO , KUBOTA SHUJI , SUGIMURA YOSHIHISA
IPC分类号： G06F9/38
摘要： PURPOSE:To provide a memory data arithmetic system and its circuit capable of reducing the size of a program at the time of consecutively processing simple calculation and reducing power consumption while improving the execution speed of the program. CONSTITUTION:When CPU 101 detects a prescribed arithmetic instruction using a memory data arithmetic circuit 100 in the program, CPU 101 releases an address bus 110 and a data bus 111 and gives an execution right to the memory data arithmetic circuit 100 by way of a control signal bus 112. As the result of this, the memory data arithmetic circuit 100 exclusively uses the address buss 110, the data bus 111 and a memory 102 and executes a prescribed calculation based on the contents of address data specified by the specified arithmetic instruction not by way of CPU 101.

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