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1. 发明专利

JPS58131851A DIFFERENTIAL LOGICAL CIRCUIT 失效
公开(公告)号：JPS58131851A
公开(公告)日：1983-08-05
申请号：JP1445182
申请日：1982-02-01
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： ITOU KIYOTOSHI , SAITOU YOUICHI , KOMAKI SHIYOUZOU
IPC分类号： H04L27/20 , H04L27/04 , H04L27/18 , H04L27/22
摘要： PURPOSE:To simplify the logical element of a logical circuit and to make the design of the circuit easy, by providing an element writing converting information setting 2 as a notation in advance to a logical operation part of a differential logical circuit and obtaining a 2 -notation output signal corresponding to a 2 -notation input code. CONSTITUTION:Transmission input codes a1-an from a transmission code input terminal 32 are written in a storage element 30 of a 2 -notation transmission logical circuit in advance as conversion information setting 2 as the natation, and the transmission input codes a1-an from the terminal 32 and a one-bit delay transmission line code from a one-bit delay element 31 are set as addresses and applied to the element 30. From an output terminal 33 of the element 30, transmission output codes b1-bn of incremental logical conversion information of 2 - notation corresponding to the codes a1-an are outputted. The 2 -notation reception logical circuit consists of a storage element 34 written with the conversion information in advance and a one-bit delay element 35, the input codes b1-bn from a tansmission line code input terminal 36 are converted, the codes a1-an are outputted to a reception code output terminal 27 to simplify the logical circuit.

2. 发明专利

JPS56132839A DIGITAL RADIO CIRCUIT SWITCHING SYSTEM 失效
公开(公告)号：JPS56132839A
公开(公告)日：1981-10-17
申请号：JP3630080
申请日：1980-03-24
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： ASAI KOUJI , MORITA KOUZOU , SAITOU YOUICHI
IPC分类号： H04B1/74 , H04L1/22
摘要： PURPOSE:To obtain a digital radio circuit switching system, by which a circuit is not cut off instantaneously, that is to say, the bit synchronizing frame is not out of synchronizm, at the time of switching, in the digital transmission system which is equipped with both the existing (n) and stand-by (m) circuits. CONSTITUTION:DIV is a branch power board for making the existing circuit branch to the stand-by circuit, TX SW is a sending-end parallel switch for simultaneously sending out a signal of the existing circuit to the stand-by circuit, TX DPU is a transmission code converter for inserting a circuit monitoring signal and a frame pulse, and RX DPU is a receiving code coverter for removing a circuit monitoring signal and a frame pulse, and detecting a circuit monitoring signal. Now, in case when the bits between each system are stepped out, they are pulled in by the TX DPU. And, when a fault has been detected, the fault information is sent out to the receiving end AS, and the receiving-end change-over switch RX SW is operated immediately.

3. 发明专利

JPS52136551A CARRIER WAVE REPRODUCTION UNIT 失效
公开(公告)号：JPS52136551A
公开(公告)日：1977-11-15
申请号：JP5355476
申请日：1976-05-11
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： HORIKAWA IZUMI , SAITOU YOUICHI
IPC分类号： H04L27/38 , H03D3/00
摘要： PURPOSE:To obtain a reproduction signal of good S/N with no phase error noise which contains synchronous stabilized phase state with every pi/2 radian, by using the carrier wave reproduction process circuit which is identical to that against 4-phase signal.

4. 发明专利

JPS55100770A CLOCK REGENERATING DEVICE 失效
公开(公告)号：JPS55100770A
公开(公告)日：1980-07-31
申请号：JP957279
申请日：1979-01-29
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： ARAKI MASAHARU , HORIKAWA IZUMI , SAITOU YOUICHI
IPC分类号： H04L7/033 , H04L7/02 , H04L7/027
摘要： PURPOSE:To regenerate a clock signal without any phase error by suppressing the phase jitter component of a clock signal due to the pattern of a digital signal when extracting a clock component from the digital signal itself to be transmitted. CONSTITUTION:A base-band quad digital signal is applied from delay circuit 17 to 1st clock extraction circuit 16, composed of clock extraction circuit 2, turning amplifier circuit 5 and limiter 6, and also to discrimination circuit 10 and two sequences of binary signals are regenerated by the regenerating clock signal of voltage control oscillator 9 and outputted to output terminals 18 and 19. Those outputs are converted by binary/quad converter 14 into a quad signal, which is also converted into a local digital signal by transmission-system filter 15. This signal is supplied to 2nd clock extraction circuit 22 as well as circuit 16; and outputs of 1st and 2nd clock extraction circuits are compared by a phase comparator and after the phase jitter component is removed, the output of the comparator is supplied to loop filter 8, where the phase error is removed and applied to circuit 9 as a normal clock.

5. 发明专利

JPS5484464A AMPLITUDE PHASE MODULATION COMMUNICATION SYSTEM 失效
公开(公告)号：JPS5484464A
公开(公告)日：1979-07-05
申请号：JP15276977
申请日：1977-12-19
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： HORIKAWA IZUMI , SAITOU YOUICHI
IPC分类号： H04L27/34 , H04L27/36 , H04L27/38
摘要： PURPOSE:To realize a small size for the circuit as well as secure an economical amplitude phase modulation communication by forming the transmission part with one unit of the quad-notation sum logic circuit and the reception part with one unit of the quad-notation difference logic circuit plus several units of the basic gate circuit. CONSTITUTION:The binary signal of 2 series among the 4 series is turned to the 2-series binary signal through the quad-notation difference conversion at quad- notation logic circuit 1 and then supplied to two units of multi-value converter 2 in the form of the higher-rank digits. At the same time, the binary signal of other 2 series is converted into the grey code via the exclusive logical sum with the output of circuit 1 and the supplied to each converter 2 in the form of the lower-rank digits. Thus, the quad-value signal is obtained, and the carrier wave 4 is transmitted through QAM. The reception signal undergoes multiplication detection 9 after 2-branch to obtain the 2- series quad-value signal which is then converted into the 2-series binary signal through two units of multi-value identifier 11, and the original signal is reproduced through quad-notation difference logic circuit 12. At the same time, the lower- and higher-digit signals of the output of each identifier 11 carry out exclusive logical sum operation 15 to obtain the natural binary code from the grey code, and the original signal is obtained through logic process 13.

6. 发明专利

JPS5297661A CARRIER WAVE REPRODUCTION EQUIPMENT 失效
公开(公告)号：JPS5297661A
公开(公告)日：1977-08-16
申请号：JP1389576
申请日：1976-02-13
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SAITOU YOUICHI , HORIKAWA IZUMI
IPC分类号： H04L27/227 , H03D3/00 , H04L27/38
摘要： PURPOSE:To obtain reproduction carrier wave of good S/N without increasing stabolity point of lead-in phase by providing logical circuit which generates pulse based on the information from multi-value discriminator at the specific phase time along with gate circuit which is driven by the pulse generated at the above logical circuit.

7. 发明专利

JPS6016715A TRANSVERSAL FILTER 失效
公开(公告)号：JPS6016715A
公开(公告)日：1985-01-28
申请号：JP12525083
申请日：1983-07-08
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SAITOU YOUICHI , MATSUE HIDEAKI , KOMAKI SHIYOUZOU
IPC分类号： H03H17/06
摘要： PURPOSE:To obtain a characteristic as designed by driving a shift register having M-tap by a clock having a frequency being N-times that of an input signal and reading an ROM with a tap output at the interval of (N-1) and adding the read results so as to omit a phase shift circuit and an analog adder circuit. CONSTITUTION:A clock having a frequency four times that of an input data at a signal input terminal 2 is applied to a terminal 10 and one input data is stored in four registers. Thus, an address input of each ROM is changed by the input speed of the data and the operating speed of the ROM can be as much as the speed of the input data. A signal shifted by 1/4 period of the input data is inputted sequentially to ROMs 6a-6d and a sampled value at each 1/4 period of the input data having a desired impulse response stored in each ROM is read. This is added by a full adder 12, converted into an analog signal at a DA converter 7 and outputted though a low pass filter 9.

8. 发明专利

JPS57142048A CODE ERROR RATE DISPLAY DEVICE 失效
公开(公告)号：JPS57142048A
公开(公告)日：1982-09-02
申请号：JP2674081
申请日：1981-02-27
申请人： ANRITSU ELECTRIC CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SUGANO SHINICHI , SAITOU YOUICHI
IPC分类号： H04L1/00 , H04L1/24
摘要： PURPOSE:To achieve a display in accordance with the generating state of error, by displaying a value corresponding to a code error rate from the clock pulse number when error code pulses reach a prescribed amount, in the display of the code error rate of a pulse code transmission system such as a PCM communication. CONSTITUTION:An error code pulse applied to an input 4 is counted at a counter circuit 9, and this measuring time is obtained from a counting value of a counter circuit 10 counting clock pulses applied to an input 2. When a counting value of the error code pulse of the circuit 9 is constant, e.g., 100, the count of the circuit 10 is stopped and the counting value is inputted to an error rate selection circuit 11. The circuit 11 consists of read only memories and the circuit stores the ratio of the error code pulse number to the clock pulse number, and when the corresponding storage content is selected, it is stored in a storage circuit 5. On the other hand, the number of digits of the count value of the circuit 10 is detected at a detection circuit 7 and stored in a storage circuit 8. The storage content of the storage circuits 5 and 8 is displayed at a display circuit 6.

9. 发明专利

JPS5267244A VALTIIVALUE DISCRIMINATION UNIT 失效
公开(公告)号：JPS5267244A
公开(公告)日：1977-06-03
申请号：JP14345775
申请日：1975-12-01
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： HORIKAWA IZUMI , SAITOU YOUICHI
IPC分类号： H04L25/03 , H03D1/00 , H03M5/20 , H04B3/36 , H04L27/38
摘要： PURPOSE:To obtain a multi-value discrimination unit, which eliminates logical circuit with use of n-units of binary discriminator, (n-1) units of filter plus substractor.

10. 发明专利

JPS5267243A AMPLITUDE PHASE MODULATION SIGNAL DEMODULATION UNIT 失效
公开(公告)号：JPS5267243A
公开(公告)日：1977-06-03
申请号：JP14345875
申请日：1975-12-01
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： HORIKAWA IZUMI , SAITOU YOUICHI
IPC分类号： H04L27/38 , H03D5/00
摘要： PURPOSE:To eliminate effect of inperfect phase modulation by performing subtraction action at base band using multi-value discriminator comprising amplitude asjuster, transmission route equivalent low-lange band pass filter, subtractor and binary discriminator.

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