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1. 发明专利

JPH0816361A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0816361A
公开(公告)日：1996-01-19
申请号：JP17340094
申请日：1994-07-01
申请人： NIPPON STEEL CORP
发明人： NAKAGAMI SHUICHI
IPC分类号： G11C7/00 , G06F5/06
摘要： PURPOSE:To provide the semiconductor integrated circuit device with which data can be written from the side of a data processor at high speed and various data sequences can be simultaneously handled. CONSTITUTION:Plural storage circuits 1-N of FIFO structure are provided, a write buffer 20 for writing input information from the outside at high speed is provided on the preceding stage of these storage circuits and by setting the input information to this write buffer 20, the information can be written from the data processor side at high speed even without accelerating the storage circuits 1-N themselves. Further, the various data sequences can be handled by the various storage circuits by selectively writing information to the respective storage circuits 1-N while referring to a storage circuit number '22' by holding the storage circuit block number '22' for identifying the respective storage circuits 1-N in the write buffer 20 so that the various data sequences can be simultaneously handled even without mounting plural FIFO chips.

2. 发明专利

JPH0757075A PROCESSOR ELEMENT OF ONE-CHIP PARALLEL PROCESSOR FOR PATTERN PROCESSING 失效
公开(公告)号：JPH0757075A
公开(公告)日：1995-03-03
申请号：JP22228693
申请日：1993-08-13
申请人： NIPPON STEEL CORP
发明人： TAKAYANAGI NOBUO , NAKAGAMI SHUICHI , ISHIKAWA MASATOSHI
IPC分类号： H04N7/18 , G06T1/20
摘要： PURPOSE:To enable a high functional and high speed pattern processing by making a register into a 1-bit register in the processor element of a one-chip parallel processor for pattern processing which is used for fetching the pattern information on a high speed visual sensor, etc., and processing the information at a high speed. CONSTITUTION:In a processor element 11 composed of plural sensors 12 sensing pattern information, the register of a one-chip parallel processor for pattern processing where plural processor elements 11 coupled with each picture element processing outputs of these sensors 12 or a picture element group composed of a few picture elements by 1 to 1 are integrated on an integrated circuit and a computing element, the computing element is composed of the computing element 22 of a bit serial arithmetic system and the register is composed by connecting plural 1-bit registers 21 with the computing element 22 in parallel.

3. 发明专利

JPH06237377A PICTURE INFORMATION PROCESSING UNIT 失效
公开(公告)号：JPH06237377A
公开(公告)日：1994-08-23
申请号：JP4469893
申请日：1993-02-08
申请人： NIPPON STEEL CORP
发明人： NAKAGAMI SHUICHI
IPC分类号： H04N1/40 , G06F15/80 , G06T1/20 , G06F15/66
摘要： PURPOSE:To attain economical picture processing at a high speed by using each information processing means to apply parallel processing to inputted picture information. CONSTITUTION:A sequencer 6 is provided at a position adjacent to a matrix of a picture input processing block 2 and sets a processing instruction from an instruction storage section 7 given to the picture processing unit to an instruction buffer 8. Moreover, the processing processing set to the instruction buffer 8 is decoded through an instruction decoder 9 and a control signal obtained as a result is sent to a processing element 3 of each picture input processing block 2. Then the inputted picture information is shared by plural processing units, in which the information is processed in parallel thereby allowing the picture information to be processed at a high speed, and since each processing unit is not necessarily a high speed processing unit, the cost of the processing unit is reduced.

4. 发明专利

JPH08297651A ARRAY PROCESSOR 失效
公开(公告)号：JPH08297651A
公开(公告)日：1996-11-12
申请号：JP12423095
申请日：1995-04-25
申请人： NIPPON STEEL CORP
发明人： TAKAYANAGI NOBUO , YAMADA YOSHIHIRO , NAKAGAMI SHUICHI
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177 , G06F15/80
摘要： PURPOSE: To considerably increase the number of processor elements which can be simultaneously communicated in the longitudinal and lateral directions of the array processor. CONSTITUTION: This array processor is provided with a data communication network 1 which is formed by connecting plural longitudinal direction and laterial direction buses 2a and 2b in the from of matrix, plural processor elements PE each connected to intersection 3 of the longitudinal direction and lateral direction buses 2a and 2b, plural switches 4 each interposed between the intersections 3, and controller 5 for controlling the opening/closing operations of the plural switches 4 and by electrically and arbitrarily disconnecting among the intersections 3, the array processor can be independently used for each desired block of the longitudinal direction and laterial direction buses 2a and 2b. Thus, data can be simultaneously transmitted/received in the plural blocks at the same row and the same column in the data communication network 1 constituted in the form of matrix.

5. 发明专利

JPH09147069A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND NO BATTERY TYPE RFID USING THE SAME 失效
公开(公告)号：JPH09147069A
公开(公告)日：1997-06-06
申请号：JP32406095
申请日：1995-11-17
申请人： NIPPON STEEL CORP
发明人： NAKAGAMI SHUICHI , SAWADA KIKUZO
IPC分类号： G06K17/00 , G06K19/07 , H02J17/00
摘要： PROBLEM TO BE SOLVED: To freely prepare protocols for controlling a non-contact type IC card (RFID) and to accelerate the processing speed. SOLUTION: Various kinds of controls are performed while using a CPU 21 in place of a conventional logic circuit and a part of a register file 1 provided inside the CPU 21 is directly connected through an RF signal line 8 to an FSK circuit 14 and a PSK circuit 15 as data transmitting and receiving means. Therefore, the data received by the FSK circuit 14, for example, can be directly inputted to a 15th register R15 without interposing an I/O port so that processing steps for inputting/outputting data can be reduced compared with the conventional case of inputting data through the I/O port. Besides, by changing the control program of the CPU 21 stored in an EEPROM 23, control protocols for instruction execution can be freely prepared.

6. 发明专利

JPH08212168A ARRAY PROCESSOR 失效
公开(公告)号：JPH08212168A
公开(公告)日：1996-08-20
申请号：JP3910295
申请日：1995-02-03
申请人： NIPPON STEEL CORP
发明人： TAKAYANAGI NOBUO , YAMADA YOSHIHIRO , NAKAGAMI SHUICHI
IPC分类号： G06F9/30 , G06F15/16 , G06F15/80
摘要： PURPOSE: To accelerate the processing speed of the array processor as a whole. CONSTITUTION: Each of four processor elements 1-4 in the array processor is provided with a multiplexer 17n for selecting either a carry outputted from any one of registers 15n [(n) is from 1 to 4] in its own processor element or a carry outputted from a register 15n-1 in the adjacent processor element. When data to be calculated by one processor element are turned to four bits, for example, the multiplexer 17n performs switching so that the carry output out of the adjacent processor element can be selected. Therefore, the respective digits of four-bit data can be bit-parallelly calculated while connecting the respective processor elements 1-4. Further, the operation efficiency of respective processor elements 1-4 can be kept high at all times so that the arithmetic of the entire array processor can be performed at much higher speed.

7. 发明专利

JPH06222987A READER OF SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH06222987A
公开(公告)日：1994-08-12
申请号：JP2850793
申请日：1993-01-26
申请人： NIPPON STEEL CORP
发明人： NAKAGAMI SHUICHI
IPC分类号： G06F12/02 , G06F12/08
摘要： PURPOSE:To shorten access time to discontinuous address by temporarily storing the information of an address in a sub recorder capable of high-speed reading, when there is a discontinuous part in address. CONSTITUTION:A main storage circuit 1 is a circuit for storing information corresponding to the address, and the main storage circuit 1 inputs/outputs the information through an input/output control circuit 3 to the designated address inputted from the outside by a storage control circuit 2. An address evaluation circuit 4 is connected to the storage control circuit 2, the address to be read this time is compared with the preceding address and when both of them are discontinuous, the effect is transmitted to the storage control circuit 2. The input/output control circuit 3 is connected to a sub storage circuit capable of high-speed access, and when the addresses of information to be read are discontinuous, this sub storage circuit 5 compares the first address of the discontinued part with the address stored in the sub storage circuit 5, transmits the result to the storage control circuit 2 and reads the address at high speed.

8. 发明专利

JPH08212169A ARRAY PROCESSOR 失效
公开(公告)号：JPH08212169A
公开(公告)日：1996-08-20
申请号：JP3910495
申请日：1995-02-03
申请人： NIPPON STEEL CORP
发明人： TAKAYANAGI NOBUO , NAKAGAMI SHUICHI , YAMADA YOSHIHIRO
IPC分类号： G06F9/30 , G06F13/00 , G06F15/16 , G06F15/173 , G06F15/80
摘要： PURPOSE: To reduce the total wiring area of a control signal line for controlling respective processor elements consisting of the array processor. CONSTITUTION: 1st-4th registers 1a-1d respectively provided at plural adjacent processor elements 10a-10d are respectively commonly connected so that the first registers 1a can be connected each other and the second registers 1b can be connected each other, and successively connected through read buses 3a-3d and write buses 4a-4d so that a computing element 2a in the first processor element 10a can be connected to the first register 1a and a computing element 2b in the second processor element 10b can be connected to the second register 2b. Since the registers 1a-1d respectively provided inside the respective processor elements 10a-10d can be commonly controlled, it is enough just to wire a control signal line 5 to any one of the respective processor elements 10a-10d and the total wiring area of the control signal line 5 can be reduced.

9. 发明专利

JPH08212073A SMALL PROCESSOR ELEMENT 失效
公开(公告)号：JPH08212073A
公开(公告)日：1996-08-20
申请号：JP3910195
申请日：1995-02-03
申请人： NIPPON STEEL CORP
发明人： TAKAYANAGI NOBUO , YAMADA YOSHIHIRO , NAKAGAMI SHUICHI , ISHIKAWA MASATOSHI
IPC分类号： G06F9/38 , G05B15/02 , H01L21/822 , H01L27/04
摘要： PURPOSE: To integrate more number of processor elements into a single LSI by miniaturizing every processor element. CONSTITUTION: A data read/write circuit consists of dynamic registers 1 to 4. The data stored in the registers 1 to 4 and the data on the arithmetic results of an ALU 11 are inverted and outputted, and these data are inverted again by the 1st inverters 9a and 9b and a 2nd inverter 10 and turned into the original data. In such a constitution, each of inverters 9 to 10 can function as a conventional flip-flop that is used to hold temporarily the data used for operation and also the computed data. Therefore, a processor element consists of a small number of transistors compared with a conventional processor element consisting of a static circuit. Then the circuit area of every processor element can be reduced.

10. 发明专利

JPH08212057A FULL ADDER 失效
公开(公告)号：JPH08212057A
公开(公告)日：1996-08-20
申请号：JP3910395
申请日：1995-02-03
申请人： NIPPON STEEL CORP
发明人： TAKAYANAGI NOBUO , NAKAGAMI SHUICHI , YAMADA YOSHIHIRO
IPC分类号： G06F7/50
摘要： PURPOSE: To provide a full adder which consists of a small number of transistors. CONSTITUTION: A full adder consists of an XNOR circuit 1 which inputs an augend signal An and an addend signal Bn and obtains an inverted signal of an exclusive OR, an XOR circuit 2 which inputs the signals An and Bn and obtains an exclusive OR, the 1st and 2nd switch circuits S1 and S2 which output the signal An or a carry signal Cn-1 of the immediate lower digit to the next digit as a carry signal Cn in response to the output signals of the circuits 1 and 2, and the 3rd and 4th switch circuits S3 and S4 which output the signal Cn-1 or the signal obtained by inverting the signal Cn-1 by an inverting circuit 3 as a sum output signal Sn in response to the output signals of the circuits 1 nd 2. In such a constitution, a logic circuit consisting of many transistors can be replaced with a switch circuit. Thereby, the total number of MOS transistors can be extremely decreased.

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