专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH0730650A FAULT REPORTING SYSTEM 失效
公开(公告)号：JPH0730650A
公开(公告)日：1995-01-31
申请号：JP17331993
申请日：1993-07-13
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , FUJITSU LTD , HITACHI LTD
发明人： MINAMIMURA KEIZO , SUZUKI KOJI , ITO ARATA , JINNAI NOBUYUKI , SAKAMOTO HIROYUKI , MATSUO SATOSHI , KOBASHI ICHIRO
IPC分类号： H04M3/08 , H04L12/24 , H04L12/26 , H04L12/28 , H04Q3/00
摘要： PURPOSE:To perform fault processing with a fault processor provided with the small kinds of softwares by separating the fault processing into fault processing not depending on the hardware and fault processing depending on the hardware. CONSTITUTION:Computer units 11-13 are provided with means at firmware parts 21-23 so as to prepare fault report information while distinguishing it into the two kinds of first fault report information 31 to transmit a recovery enable fault by exchanging the hardware and second fault report information 32 to transmit a recovery disable fault by exchanging the hardware. A fault processor 7 is provided with a means at a CPU 10 so as to first process the first fault report information 31 and to process the second fault report information 32 later when the fault can not be recovered. Thus, the kinds of memory means for storing the fault processing softwares and the fault processing softwares can be reduced, and countermeasures at the time of generating the fault can be speedily executed.

2. 发明专利

JPH0738573A TEST SYSTEM FOR ATM EXCHANGE AND ATM NETWORK 失效
公开(公告)号：JPH0738573A
公开(公告)日：1995-02-07
申请号：JP18270693
申请日：1993-07-23
申请人： NIPPON TELEGRAPH & TELEPHONE , NEC CORP , HITACHI LTD , OKI ELECTRIC IND CO LTD , FUJITSU LTD
发明人： TAKAGI KOJI , ITO ARATA , MIYAYASU KENJI , TAKENAKA TOYOFUMI , SUZUKI KOJI , SHIBATA JIRO , SHIMOE TOSHIO , SAKAMOTO HIROYUKI
IPC分类号： H04Q3/00 , H04L12/26 , H04L12/28
摘要： PURPOSE:To improve the reliability and performance of an ATM exchange and an ATM network by efficiently testing active and reserve systems. CONSTITUTION:Concerning the test system for ATM exchange and ATM network composed of that ATM exchange or the like provided with plural function blocks 1-6 made redundant into the active and reserve system so as to transfer cells and plural system crossings 20 and 21 for performing path setting between the respective function blocks, this system is provided with first system crossing control parts 101 and 103 for setting a path between the respective function blocks of the reserve system independently of the path of the active system by controlling the system crossings 20 and 21, and a test circuit 200 for performing the cell conduction test of the reserve system to which path setting is performed based on the control of these first system crossing control parts 101 and 103, and the reserve system is tested while providing service at the active system.

3. 发明专利

JPH06303400A DATA TRANSMISSION SYSTEM 失效
公开(公告)号：JPH06303400A
公开(公告)日：1994-10-28
申请号：JP11205893
申请日：1993-04-15
申请人： NITSUKO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SAKAMOTO HIROYUKI , YUZA MASAAKI , SUGIYAMA AKINARI , IDE TOSHIKAZU , KONDO KOICHI , TANAKA KOJI , SHIROKURA TORU , IGUCHI MIKAKO , TAKASHIMA TETSUO
IPC分类号： H04N1/21
摘要： PURPOSE:To transmit the large amount of data with a small storage capacity by relating the storage capacity of a source data storage device with the storage capacity of an encoded data storage device. CONSTITUTION:The source data storage device 1 on a transmission side 10 and a reception side 20 is provided with the storage capacity A for which a quotient for which the storage capacity B of the encoded data storage device is divided by the compressibility of a maximum encoding pattern is subtracted from a source data amount by the portion of one screen. Read source data are encoded by an encoding/decoding device 2 and transmitted. The transmitted encoded data are received on the reception side 20, decoded by the encoding/ decoding device 2 and turned to the source data. When the encoded data storage device 3 on the reception side 20 becomes full and incapable of reception, the reception side 20 sends the report of reception incapability and the transmission side 10 transmits the data which could not be transmitted later again.

4. 发明专利

JPH03211939A ROUTE SELECTING SYSTEM FOR PACKET SWITCHING SWITCH 失效
公开(公告)号：JPH03211939A
公开(公告)日：1991-09-17
申请号：JP623690
申请日：1990-01-17
申请人： OKI ELECTRIC IND CO LTD
发明人： ARAKAWA NOBUYA , MASAKI TATSUYA , JIN YOSHIHIRO , SAKAMOTO HIROYUKI
IPC分类号： H04L12/70 , H04L12/729
摘要： PURPOSE:To decrease block generation to the call of a high-speed packet and to improve the throughput of a switching network as a whole by selecting a communication route optimum for the speaking amount of the call out of all the searched routes. CONSTITUTION:When the call is set, the communication route to transfer the call is searched as a route candidate and according to the link using amount of the searched route candidate and the speaking amount of the call, the evaluation value of the route candidate is calculated for showing difference between capacity to be used by the call and the idle capacity of the route candidate. Then, the route with the minimum evaluation value is selected as the communication route to transfer the call. Thus, the generation rate of the block in packet transfer can be suppressed at a minimum.

5. 发明专利

JPH0298246A PACKET EXCHANGE 失效
公开(公告)号：JPH0298246A
公开(公告)日：1990-04-10
申请号：JP24993388
申请日：1988-10-05
申请人： OKI ELECTRIC IND CO LTD
发明人： SAKAMOTO HIROYUKI , KIMURA HIROSHI
IPC分类号： H04L12/18 , H04L12/64 , H04L12/70
摘要： PURPOSE:To attain the multiple address of a packet even in a general terminal interface without the need of any exclusive terminal interface circuit for multiple address by storing multiple address instruction information representing the presence of multiple address packet and setting the multiple address instruction information by a control processor when the information representing the implementation of multiple address is received from a terminal equipment. CONSTITUTION:A packet switch circuit 40 applying switching of a packet is provided and a switching header addition circuit 50 adds a header 52 to a packet to form an internal packet transferred in the inside of an exchange. A control processor 100 controls circuits such as the packet switch circuit, the switching header addition circuit 50 and a terminal interface circuit 10 and when a terminal equipment 1 sends information representing the implementation of the multiple address together with a message, the information is received from a packet conversion circuit 11 to set a multiple address storage memory 55. Thus, it is not required to provide a terminal interface circuit exclusive for use of multiple address and the multiple address processing is implemented.

6. 发明专利

JP2523173B2 失效
公开(公告)号：JP2523173B2
公开(公告)日：1996-08-07
申请号：JP1630489
申请日：1989-01-27
申请人： OKI ELECTRIC IND CO LTD
发明人： JIN YOSHIHIRO , ARAKAWA NOBUYA , MASAKI TATSUYA , SAKAMOTO HIROYUKI
IPC分类号： H04L12/823 , H04L12/851 , H04L12/861 , H04L12/935 , H04L12/56

7. 发明专利

JPH0496545A ASYNCHRONOUS TRANSFER MODE EXCHANGE METHOD AND ASYNCHRONOUS TRANSFER MODE EXCHANGE AND SWITCHING CIRCUIT 失效
公开(公告)号：JPH0496545A
公开(公告)日：1992-03-27
申请号：JP21374790
申请日：1990-08-14
申请人： OKI ELECTRIC IND CO LTD
发明人： MASAKI TATSUYA , UETAKE YOSHIKATSU , HAYASHI KENTARO , SAKAMOTO HIROYUKI
摘要： PURPOSE:To make internal configuration of a logic switch of each stage coincident and to make each stage in common by using the logic switch of each stage to read each logic code of a switching header and shifting the code to the tail end of the switching header. CONSTITUTION:A logic switch 300 is switched according to a head bit of a switching header HD inputted from a pre-stage header shift circuit 400 to decide an output destination of a next stage, a header shift means 400 shifts a head bit of a switching header HD to a tail end of the switching header HD and the bit to be read by a next stage logic switch 300 is transferred to a next stage while the bit is brought to a top. Thus, a header shift circuit 400 of each stage makes the same operation that the head bit is transferred to a tail end of the switching header HD and a logic switch 300 of each stage reads only the head bit of the switching header HD and is switched to transfer a cell.

8. 发明专利

JPH02284545A METHOD AND DEVICE FOR DETECTING FAULT OF HARDWARE SWITCH 失效
公开(公告)号：JPH02284545A
公开(公告)日：1990-11-21
申请号：JP10458789
申请日：1989-04-26
申请人： OKI ELECTRIC IND CO LTD
发明人： JIN YOSHIHIRO , MASAKI TATSUYA , SAKAMOTO HIROYUKI , ARAKAWA NOBUYA
IPC分类号： H04L12/70 , H04L12/931
摘要： PURPOSE:To eliminate the needs for generating a test pattern and the expected result of an output corresponding to the test pattern and to enable the on-line test by storing the switching state of switches in a 'NEMAWASHI' batcher network (a switch using a hardware scheduler for a packet switching device, etc.) and an exchange batcher network and comparing them. CONSTITUTION:When exchange data arrive at input timing T0-T7, they are taken into an input buffer 50, and the 'NEMAWASHI' batcher network 100 sorts the data. A winning notice part 300 executes decision and the result is returned to the buffer 50. Normally, 'NEMAWASHI' is executed for several times. In the exchange batcher network 200, a packet pass through respective exchange cells Celx, y and the switching state of respective exchange cells Celx, y is stored in corresponding state holding memories Smx, y. After the packets have passed through the exchange batcher network 200, a comparison part(COMP) 400 compares the contents (switching direction) of the state holding memories Smx, y of the 'NEMAWASHI' batcher network 100 with the content of the state holding memories Smx, y of the exchange batcher network 200 corresponding to respective rows and columns. Thus, whether the 'NEMAWASHI' batcher network 100 and the exchange batcher network 200 are switch-operated in the same direction or not is compared.

9. 发明专利

JPH02198248A PACKET EXCHANGE SWITCH DEVICE 失效
公开(公告)号：JPH02198248A
公开(公告)日：1990-08-06
申请号：JP1630489
申请日：1989-01-27
申请人： OKI ELECTRIC IND CO LTD
发明人： JIN YOSHIHIRO , ARAKAWA NOBUYA , MASAKI TATSUYA , SAKAMOTO HIROYUKI
IPC分类号： H04L12/823 , H04L12/851 , H04L12/861 , H04L12/935
摘要： PURPOSE:To attain effective transmission to a packet exchange switch even when transmission awaiting queue is in congestion by storing once a priority packet to a buffer circuit and awaiting the transmission of a transmission queue till idle transmission waiting queue takes place. CONSTITUTION:Priority packet discrimination circuits 111-11n discriminate whether packets A-N reaching input terminals 101-10n are packets with priority or non-priority packets depending on the presence of designated information and output a switching signal to pre-stage selectors 121-12n. The selectors 121-12n use a switching signal of the circuits, 111-11n to switch packet paths 201-20n from bypass circuits 181-18n to buffer circuits 131-13n to store the priority packet via the circuits 111-11n to the circuits 131-13n. Moreover, in the absence of a switching signal, since the reached packet is non-priority packets, the packet is sent to the circuits 181-18n as it is.

10. 发明专利

JPH01166644A BUFFER MANAGEMENT SYSTEM 失效
公开(公告)号：JPH01166644A
公开(公告)日：1989-06-30
申请号：JP32384287
申请日：1987-12-23
申请人： OKI ELECTRIC IND CO LTD
发明人： SAKAMOTO HIROYUKI , FUJIKAWA FUYUKI
摘要： PURPOSE:To attain packet management with a simple constitution by providing a means comparing a readout time with a time when a packet is written in a buffer in case of reading the packet from the buffer. CONSTITUTION:An arrival time (t1) is added at a time addition device 3 to a packet arrived from a terminal/exchange interface section 6 to a packet exchange section 1 and the result is stored in a buffer memory 4. On the other hand, in case of the transfer of a packet from the exchange section 1 to a terminal/exchange interface section 7, the time t1 when the packet is stored in the memory 4 and a present time (t2) are compared by a time comparator 5. When a value (t2-t1) is a prescribed time or below as a result, the packet is transferred to the interface section 7, and when the value is the prescribed value or above, the packet is aborted.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式