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1. 发明专利

JPH03255748A PACKET ORDER ARRANGING SYSTEM 失效
公开(公告)号：JPH03255748A
公开(公告)日：1991-11-14
申请号：JP5284590
申请日：1990-03-06
申请人： OKI ELECTRIC IND CO LTD
发明人： HAYASHI KENTARO , ARAKAWA NOBUYA , KIMURA HIROSHI , MASAKI TATSUYA
IPC分类号： H04L12/70
摘要： PURPOSE:To accelerate packet transfer by transferring a transmission packet while adding a time stamp on the transmission side, and outputting the packet in the order of the time stamp on the reception side. CONSTITUTION:In a packet switching network 101, a time imparting circuit 100 is provided on the side of plural incoming lines 120-12M in the packet, and plural correspondent packet order arrangers 110-11N are provided on the side of plural outgoing lines 130-13N. On the incoming side of the packet switching network 101, the input packet is outputted while imparting the time stamp of a turning number by the time imparting means 100, and on the outgoing side, the order arranging means 110-11N transfer the packets to the outgoing lines 130-13N in the order of the time stamp numbers. Therefore, the order arranging means 110-11N can correctly identify the time sequence of the time stamps.

2. 发明专利

JPH02213248A REDUNDANT CONSTITUTION SYSTEM 失效
公开(公告)号：JPH02213248A
公开(公告)日：1990-08-24
申请号：JP3278789
申请日：1989-02-14
申请人： OKI ELECTRIC IND CO LTD
发明人： SAKAMOTO HIROYUKI , MASAKI TATSUYA , ARAKAWA NOBUYA , JIN YOSHIHIRO
IPC分类号： H04M3/22 , H04Q1/24 , H04Q11/04
摘要： PURPOSE:To offer a system with high reliability by forming a system with a constituent having a fault avoidance circuit and adapting it to be of redundant constitution. CONSTITUTION:A fault detection control circuit 2 is a control circuit which replaces a switch network 1A with a fault avoidance circuit operated as an active system in the case of being faulty into a switch network 1B with a fault avoidance circuit in standby as a standby system and when a fault of the active system switch network 1 is detected from an input line 112, system changeover switches 3 and 4 control to apply the system switching processing. Thus, the equipment with high reliability is offered.

3. 发明专利

JPH03211939A ROUTE SELECTING SYSTEM FOR PACKET SWITCHING SWITCH 失效
公开(公告)号：JPH03211939A
公开(公告)日：1991-09-17
申请号：JP623690
申请日：1990-01-17
申请人： OKI ELECTRIC IND CO LTD
发明人： ARAKAWA NOBUYA , MASAKI TATSUYA , JIN YOSHIHIRO , SAKAMOTO HIROYUKI
IPC分类号： H04L12/70 , H04L12/729
摘要： PURPOSE:To decrease block generation to the call of a high-speed packet and to improve the throughput of a switching network as a whole by selecting a communication route optimum for the speaking amount of the call out of all the searched routes. CONSTITUTION:When the call is set, the communication route to transfer the call is searched as a route candidate and according to the link using amount of the searched route candidate and the speaking amount of the call, the evaluation value of the route candidate is calculated for showing difference between capacity to be used by the call and the idle capacity of the route candidate. Then, the route with the minimum evaluation value is selected as the communication route to transfer the call. Thus, the generation rate of the block in packet transfer can be suppressed at a minimum.

4. 发明专利

JPH04838A BUFFER CONTROL SYSTEM 失效
公开(公告)号：JPH04838A
公开(公告)日：1992-01-06
申请号：JP9942090
申请日：1990-04-17
申请人： OKI ELECTRIC IND CO LTD
发明人： SAKAMOTO HIROYUKI , MASAKI TATSUYA , HAYASHI KENTARO , UETAKE YOSHIKATSU
IPC分类号： H04L12/28 , H04L12/70 , H04L12/835 , H04L12/56
摘要： PURPOSE:To make preferential processing of a preliminary selection packet from the packet having the largest buffer using amount possible so as to make a packet arriving at a buffer not easily discarded even when the capacity of the buffer is not increased by incorporating the using status of the buffer in preliminary selection packet information. CONSTITUTION:A switch 26 which is a self-routing multi-stage switching network is provided with packet buffers 220-227 and input ports 100-107 are respectively connected to the input side of the switch 26. A preliminary selection and main selection networks 24 and 25 are connected in parallel to the output side of the switch 26. Output ports 130-137 are connected to the output side of the network 25. The packet buffer 220 is constituted of a buffer controlling section 201, buffer 202, buffer using amount detection circuit 203, and preliminary selection packet assemble circuit 204 and outputs packets to be inputted to the switch 26 after tentatively accumulating the packets and giving buffer using amount indicating bits to the packets. Upon inputting the packets, the network 26 preferentially processes the packets having larger buffer using amounts so as to prevent the packets from being discarded at an input buffer.

5. 发明专利

JPH02205138A FAULT DETECTION CIRCUIT FOR BATCHER NETWORK 失效
公开(公告)号：JPH02205138A
公开(公告)日：1990-08-15
申请号：JP2381289
申请日：1989-02-03
申请人： OKI ELECTRIC IND CO LTD
发明人： MASAKI TATSUYA , JIN YOSHIHIRO , SAKAMOTO HIROYUKI , ARAKAWA NOBUYA
IPC分类号： G06F7/24 , H04Q1/24
摘要： PURPOSE:To detect a sorting error with a small hardware configuration by comparing the size relation of two output adjacent to each other in a batcher network. CONSTITUTION:Signals adjacent to each other out of the signals outputted from output lines 101-104 are inputted to the comparators 51-53 of a fault detection circuit 11. At this time, when the sorting error due to the fault of batcher element 41, 22, or 32 occurs, the signal from the output line 111 of the comparator 51 or the output line 112 of the comparator 52 goes to a high level. Therefore, output from an OR gate 61 also goes to the high level, and it is outputted from the output line 131 of the fault detection circuit 11 as a detecting signal. In such a manner, it is possible to inform the existence of the sorting error in a device at an output destination by using the detecting signal from the fault detection circuit 11 when the fault occurs in either batcher elements.

6. 发明专利

JPH01170193A REMOTE CONTROL SYSTEM FOR EXCHANGE 失效
公开(公告)号：JPH01170193A
公开(公告)日：1989-07-05
申请号：JP32676487
申请日：1987-12-25
申请人： OKI ELECTRIC IND CO LTD
发明人： MASAKI TATSUYA
IPC分类号： H04M3/22 , H04Q3/545
摘要： PURPOSE:To execute the centralized management of each station of a switching network by transmitting a remote control signal from a remote control exchange to an exchange to be controlled, and remote-controlling the exchange to be controlled. CONSTITUTION:At the time of remote-controlling an exchange 200 to be controlled from a remote control exchange 220, the remote control exchange 220 makes a remote control command into a packet by a packet transmitting and receiving circuit 201, and it is transmitted to a transmission line 210. A remote control identifying device 300 of the exchange 200 to be controlled converts the received remote control command to parallel data by a parallel/serial converting circuit 303, and the data are outputted to a pattern identifying circuit 304. When the received command coincides with a prescribed pattern, for example, the pattern of an emergency activating instruction, the pattern identifying circuit 304 outputs the emergency activation instructing signal through a signal converting circuit 305 to a control line 313, and the switching control of the exchange 200 to be controlled is executed.

7. 发明专利

JPH01137747A PACKET SWITCHING SYSTEM 失效
公开(公告)号：JPH01137747A
公开(公告)日：1989-05-30
申请号：JP29503587
申请日：1987-11-25
申请人： OKI ELECTRIC IND CO LTD
发明人： KIMURA HIROSHI , MASAKI TATSUYA
摘要： PURPOSE:To make the periodical switching of a system for detecting a latent fault in a system switch in waiting unnecessary and to prevent the concentration of loads on one system switch only by providing first and second switches with a routing adding means and a gate means, etc. CONSTITUTION:In a packet switching equipment consisting of the first zero- system switch 11 and the second one-system switch 12, the routing adding circuit 12, the packet gate circuit 15, and a switch circuit 17 are provided respectively to the switches 11, 12. The respective circuits 13, upon receiving a packet from a terminal A or B, adds opposite's destination information and a packet act bit supplied from a control part 23 to the packet, and transmits the result to the packet gate circuit 15. The circuit 15 judges the validity of the packet received from the circuit 13 by using the packet act bit and the act signal 21, 22; in case it is valid, the circuit 15 transmits the packet to the switch circuit 17, but in case it is invalid, the packet is abandoned. As a result, the periodic switching between the systems can be made unnecessary, the concentration of loads on one system switch can be prevented, and the reliability can be improved.

8. 发明专利

JP2523173B2 失效
公开(公告)号：JP2523173B2
公开(公告)日：1996-08-07
申请号：JP1630489
申请日：1989-01-27
申请人： OKI ELECTRIC IND CO LTD
发明人： JIN YOSHIHIRO , ARAKAWA NOBUYA , MASAKI TATSUYA , SAKAMOTO HIROYUKI
IPC分类号： H04L12/823 , H04L12/851 , H04L12/861 , H04L12/935 , H04L12/56

9. 发明专利

JPH0496545A ASYNCHRONOUS TRANSFER MODE EXCHANGE METHOD AND ASYNCHRONOUS TRANSFER MODE EXCHANGE AND SWITCHING CIRCUIT 失效
公开(公告)号：JPH0496545A
公开(公告)日：1992-03-27
申请号：JP21374790
申请日：1990-08-14
申请人： OKI ELECTRIC IND CO LTD
发明人： MASAKI TATSUYA , UETAKE YOSHIKATSU , HAYASHI KENTARO , SAKAMOTO HIROYUKI
摘要： PURPOSE:To make internal configuration of a logic switch of each stage coincident and to make each stage in common by using the logic switch of each stage to read each logic code of a switching header and shifting the code to the tail end of the switching header. CONSTITUTION:A logic switch 300 is switched according to a head bit of a switching header HD inputted from a pre-stage header shift circuit 400 to decide an output destination of a next stage, a header shift means 400 shifts a head bit of a switching header HD to a tail end of the switching header HD and the bit to be read by a next stage logic switch 300 is transferred to a next stage while the bit is brought to a top. Thus, a header shift circuit 400 of each stage makes the same operation that the head bit is transferred to a tail end of the switching header HD and a logic switch 300 of each stage reads only the head bit of the switching header HD and is switched to transfer a cell.

10. 发明专利

JPH02284545A METHOD AND DEVICE FOR DETECTING FAULT OF HARDWARE SWITCH 失效
公开(公告)号：JPH02284545A
公开(公告)日：1990-11-21
申请号：JP10458789
申请日：1989-04-26
申请人： OKI ELECTRIC IND CO LTD
发明人： JIN YOSHIHIRO , MASAKI TATSUYA , SAKAMOTO HIROYUKI , ARAKAWA NOBUYA
IPC分类号： H04L12/70 , H04L12/931
摘要： PURPOSE:To eliminate the needs for generating a test pattern and the expected result of an output corresponding to the test pattern and to enable the on-line test by storing the switching state of switches in a 'NEMAWASHI' batcher network (a switch using a hardware scheduler for a packet switching device, etc.) and an exchange batcher network and comparing them. CONSTITUTION:When exchange data arrive at input timing T0-T7, they are taken into an input buffer 50, and the 'NEMAWASHI' batcher network 100 sorts the data. A winning notice part 300 executes decision and the result is returned to the buffer 50. Normally, 'NEMAWASHI' is executed for several times. In the exchange batcher network 200, a packet pass through respective exchange cells Celx, y and the switching state of respective exchange cells Celx, y is stored in corresponding state holding memories Smx, y. After the packets have passed through the exchange batcher network 200, a comparison part(COMP) 400 compares the contents (switching direction) of the state holding memories Smx, y of the 'NEMAWASHI' batcher network 100 with the content of the state holding memories Smx, y of the exchange batcher network 200 corresponding to respective rows and columns. Thus, whether the 'NEMAWASHI' batcher network 100 and the exchange batcher network 200 are switch-operated in the same direction or not is compared.

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