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1. 发明专利

JP2001238279A CHANNEL APPARATUS AND INTERFACE UNIT 失效
公开(公告)号：JP2001238279A
公开(公告)日：2001-08-31
申请号：JP2000048891
申请日：2000-02-21
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD , OKI ELECTRIC IND CO LTD , NEC CORP
发明人： OBAYASHI JUNYA , MORIWAKI NORIHIKO , DOI YUKIHIRO , GENDA KOICHI , KOBAYASHI TAKAFUMI , MATSUO SATOSHI , TSUCHIDA TOMOHIRO , NOGUCHI HIROSHI , SATO DAISUKE
IPC分类号： H04Q3/42 , H04Q1/02 , H04Q11/04
摘要： PROBLEM TO BE SOLVED: To provide a channel apparatus that can easily change a redundancy form of a line adaptor section with a high mount density. SOLUTION: In the cannel apparatus where switch sections are made redundant, each interface unit comprises 1st and 2nd group line adaptor sections, at least a couple of switch interfaces where line adaptor sections are multiplexed to be coupled with an active system or standby switch section, and a back wiring board(BWB) that forms connection wiring between each line adaptor section and each switch interface. The BWB has a wiring pattern for the case that the 1st group line adaptor section is used for the active system and the 2nd group line adaptor section is used for the standby system and has a wiring pattern for the case that all the line adaptor sections are used for the active system and each the 2nd group line adaptor section is provided with an input selection means that validates a part of the connection wirings on the BWB in response to the application form and invalidates the rest.

2. 发明专利

JPH0730650A FAULT REPORTING SYSTEM 失效
公开(公告)号：JPH0730650A
公开(公告)日：1995-01-31
申请号：JP17331993
申请日：1993-07-13
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , FUJITSU LTD , HITACHI LTD
发明人： MINAMIMURA KEIZO , SUZUKI KOJI , ITO ARATA , JINNAI NOBUYUKI , SAKAMOTO HIROYUKI , MATSUO SATOSHI , KOBASHI ICHIRO
IPC分类号： H04M3/08 , H04L12/24 , H04L12/26 , H04L12/28 , H04Q3/00
摘要： PURPOSE:To perform fault processing with a fault processor provided with the small kinds of softwares by separating the fault processing into fault processing not depending on the hardware and fault processing depending on the hardware. CONSTITUTION:Computer units 11-13 are provided with means at firmware parts 21-23 so as to prepare fault report information while distinguishing it into the two kinds of first fault report information 31 to transmit a recovery enable fault by exchanging the hardware and second fault report information 32 to transmit a recovery disable fault by exchanging the hardware. A fault processor 7 is provided with a means at a CPU 10 so as to first process the first fault report information 31 and to process the second fault report information 32 later when the fault can not be recovered. Thus, the kinds of memory means for storing the fault processing softwares and the fault processing softwares can be reduced, and countermeasures at the time of generating the fault can be speedily executed.

3. 发明专利

JP2000115273A DATA TRANSFER EQUIPMENT 失效
公开(公告)号：JP2000115273A
公开(公告)日：2000-04-21
申请号：JP27811198
申请日：1998-09-30
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： YOKOUCHI HIDEAKI , MINAMIMURA KEIZO , GENDA KOICHI , OMOTANI MASAAKI , SUZUKI KAZUYUKI , MATSUO SATOSHI , UCHINO KENICHI
IPC分类号： G06F13/38 , G06F1/12 , H04L25/02 , H04L25/40 , H04L29/02
摘要： PROBLEM TO BE SOLVED: To reduce the number of terminals of an LSI or a printed board by making a clock signal and a synchronous signal of a control information signal common with a clock signal and a synchronous signal of a user information signal. SOLUTION: This data transfer equipment is provided with a cell data transmission processing part 20 on a master side to transmit and receive a user information signal, a cell data reception processing part 23 at the master side, a control bus transmission control part 22 on the master side to transmit and receive the control information signal and a control bus reception control part 28 at the master side. And the clock signal and the synchronizing signal of the control information signal are made common with the clock signal and the synchronizing signal of the user information signal. Namely, a cell transmission clock signal and a cell synchronizing signal are used as a clock signal for transmission of the control signal and a synchronizing signal for the control signal when the control bus signal is transmitted by the control bus transmission control part 22 on the master side. Therefore, the cell transmission clock signal and the cell synchronizing signal are supplied to the control bus transmission control part 22 at the master side as the control bus synchronizing signal 21 by the cell data transmission processing part 20 on the master side.

4. 发明专利

JP2000031971A LINE ADAPTOR 失效
公开(公告)号：JP2000031971A
公开(公告)日：2000-01-28
申请号：JP19289998
申请日：1998-07-08
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD
发明人： AMANO MITSUHARU , TOMONAGA HIROSHI , SUZUKI KAZUYUKI , MATSUO SATOSHI , OMOTANI MASAAKI , GENDA KOICHI , DOI YUKIHIRO , WATABE KAZUO , TSUCHIDA TOMOHIRO
IPC分类号： H04L1/22 , H04L12/28 , H04L12/70 , H04L12/713 , H04L12/775 , H04L12/935 , H04Q3/00
摘要： PROBLEM TO BE SOLVED: To prevent missing, duplication of cells and inversion of cell sequence in a switching state of a duplicate system in the case that the line adaptor provided to an ATM exchange, and composed of active/standby systems adds system identification information to a cell received by each system, writes the cell to a storage means, and reads the cell therefrom and outputs it. SOLUTION: The line adaptor 100 is provided with a read end detection means 110 that monitors cells arriving before switching which have been stored in storage means 102 of both the systems and detects that all the cells having arrived before switching are read when receiving an instruction externally to switch an operating state of both systems. An each-system identifier addition means 101 revises system identification information to be added to each cell, with a read stop means 120 that stops reading of cells stored in the storage means when the means 110 detects that all the cells having arrived before switching are read, and a read restart means 130 that restores reading of cells stored in each storage means when the means 120 stops reading of the cells stored in the storage means 102 of both the systems.

5. 发明专利

JP2002271370A IP OVER ATM SWITCH AND IP OVER ATM NETWORK SYSTEM 失效
公开(公告)号：JP2002271370A
公开(公告)日：2002-09-20
申请号：JP2001062453
申请日：2001-03-06
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MATSUO SATOSHI , OMOTANI MASAAKI , SHIOMOTO KOHEI
IPC分类号： H04L12/931 , H04L12/947 , H04L12/951 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To autonomously control the internal pass which is set in an IP over ATM switch by hardware. SOLUTION: With respect to each sub unit 101 on the input side, an internal pass control means 112 allocates an adequate pass identifier to each combination of input source information and destination information stored in its own unit for preparing an internal pass table 111. An internal conversion means 114 searches for information including the corresponding internal pass identifier from the internal pass table 111 according to the combination of the destination information and the input source information which is detected by a destination information detecting means 113. The internal conversion means 114 converts headers included in a series of ATM cells by using the information and inputs them to a switch circuit. At each sub unit 103 on the output side, a conversion control means 116 prepares a header conversion table 115 according to the information concerning pass between nodes, and provides it for header conversion process by a header conversion means 117.

6. 发明专利

JPH10107807A ATM SWITCH 失效
公开(公告)号：JPH10107807A
公开(公告)日：1998-04-24
申请号：JP26207596
申请日：1996-10-02
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： KURIMOTO TAKASHI , GENDA KOICHI , YAMANAKA NAOAKI , MATSUO SATOSHI , TOMONAGA HIROSHI
IPC分类号： H04L12/931 , H04L12/28 , H04L12/947 , H04Q3/00
摘要： PROBLEM TO BE SOLVED: To reduce a manufacture cost and a maintenance/management cost by providing an input copy part provided with a means for imparting routing information to a duplicated cell and a switch part for connecting input/output channels in 1:1 correspondence. SOLUTION: In the input copy/header conversion tables 64-1-64-4 of the input copy parts 60-1-60-4, the routing information to a plurality of predetermined output channels 50-1-50-4 corresponding to the destination information of an arriving cell and the duplication number of the cell for performing distribution to the output channels 50-1-50-4 are recorded. In input copy/header conversion processing parts 61-1-61-4, the cell is duplicated corresponding to the input copy/header conversion tables 64-1-64-4 and the pertinent routing information is imparted to the cell duplicated corresponding to the input copy/header conversion tables 64-1-64-4. Then, the switch part 100 connects the input/output channels in the 1:1 correspondence corresponding to the routing information.

7. 发明专利

JP2001345824A TAG-CONVERTING DEVICE 失效
公开(公告)号：JP2001345824A
公开(公告)日：2001-12-14
申请号：JP2000168367
申请日：2000-06-06
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SUZUKI KAZUYUKI , MATSUO SATOSHI , OMOTANI MASAAKI , SENMARU TAKESHI
IPC分类号： H04L12/28
摘要： PROBLEM TO BE SOLVED: To provide a tag converting device, with which the loss of cells does not occur, when switching from an active system to a reserve system. SOLUTION: A first packet synthesizing means 1 and a second packet synthesizing means 2 generate first and second packets by synthesizing inputted cells. When switching of the active system and the reserve system is requested, a selection information generating means 3 generates selection information showing which of first and second packets is to be selected. A first packet disassembling means 4 and a second packet disassembling means 5 generate the first and second cells by disassembling the first and second packets. A first cell storage means 6 and a second cell storage means 7 store the first and second cells separately for each class of these cells. A first cell read means 8 and a second cell read means 9 successively read out the first and second cells stored in the first and second cell storage means for each class, and when the selection information is generated by the selection information generating means 3, the timing for reading out the cells is controlled according to the control of a timing control means 10.

8. 发明专利

JP2001144801A HEADER CONVERSION DEVICE AND FRAME TRANSFER DEVICE 失效
公开(公告)号：JP2001144801A
公开(公告)日：2001-05-25
申请号：JP31976399
申请日：1999-11-10
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MATSUO SATOSHI , KOTANI KUNIHIRO , SHIOMOTO KOHEI , UGA MASANORI
IPC分类号： H04L12/741 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide a header conversion device which can speed up a processing while the cost riser of parts application is suppressed. SOLUTION: A header retrieval processing part 110 has n-pieces of retrieval parts 112-1 to 112-n which can be operated in parallel and it retrieves a MAC address corresponding to the transfer destination device of a frame, based on a destination IP address included in the inputted frame. A retrieval result is sent to a header conversion processing part 140 together with the writing address and the frame length of the frame with respect to a frame buffer 130. The header conversion processing part 140 executes a header conversion processing for substituting the destination MAC address in a MAC header included in the frame which is read from the frame buffer 130 for the destination MAC address as the retrieval result, which is outputted from the header retrieval processing part 110, and sequentially outputs the frames after a header conversion processing from a header conversion device 100.

9. 发明专利

JP2000013397A ATM EXCHANGE 失效
公开(公告)号：JP2000013397A
公开(公告)日：2000-01-14
申请号：JP17889498
申请日：1998-06-25
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TOMONAGA HIROSHI , MATSUOKA NAOKI , AMANO MITSUHARU , MATSUO SATOSHI , OMOTANI MASAAKI , GENDA KOICHI , DOI YUKIHIRO
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To allow a virtual connection VC shaper to apply VC shaping only to a VC requiring shaping in the case that the VC shaper is provided to conduct VS/VD control. SOLUTION: A class VC distribution section 61 discriminates an input cell to decide whether a cell with a priority class is directly outputted or distributed to a corresponding buffer 62x or a cell of other VC shaping class and non- priority class is distributed to corresponding distribution buffers 62y, 62z. A control section 70 outputs cells with priority in the order of the priority class, the VC shaping class and the non-priority class.

10. 发明专利

JP2004015561A Packet processing device 有权
公开(公告)号：JP2004015561A
公开(公告)日：2004-01-15
申请号：JP2002167753
申请日：2002-06-07
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MATSUO SATOSHI , NISHIMURA NORIHISA
IPC分类号： H04L12/701 , H04L12/773 , H04L12/775 , H04L12/865 , H04L12/869 , H04L12/879 , H04L29/06 , H04L12/56
CPC分类号： H04L45/60 , H04L45/742 , H04L45/7453 , H04L47/20 , H04L47/24 , H04L49/90 , H04L49/901 , H04L69/22
摘要： PROBLEM TO BE SOLVED: To improve the throughput of a packet processing device by significantly suppressing a waiting time for retrieval.
SOLUTION: The packet processing device is provided with a retrieval engine containing an associative memory for transferring a packet based on an entry corresponding to route information, a first processor which performs retrieval before packet processing is transferred to the retrieval engine, and a second processor which performs relay retrieval for relaying the packet based on the retrieved result of the retrieval engine. In this constitution, a table is also provided to transfer information between the first processor which performs the retrieval and the second processor which performs the relay retrieval, and identification information at a specific place of the table is transferred by using the retrieval engine as a transmitting medium.
COPYRIGHT: (C)2004,JPO

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