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1. 发明专利

JP2508818B2 失效
公开(公告)号：JP2508818B2
公开(公告)日：1996-06-19
申请号：JP24934788
申请日：1988-10-03
申请人： MITSUBISHI ELECTRIC CORP
发明人： KOMORI SHIGEKI , TSUKAMOTO KATSUHIRO
IPC分类号： H01L21/225 , H01L21/265 , H01L21/285 , H01L21/336 , H01L29/78

2. 发明专利

JPH06163844A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06163844A
公开(公告)日：1994-06-10
申请号：JP31711092
申请日：1992-11-26
申请人： MITSUBISHI ELECTRIC CORP
发明人： MAMETANI TOMOHARU , SHIMIZU MASAHIRO , TSUKAMOTO KATSUHIRO , ARAI HAJIME , KOBAYASHI HEIJI
IPC分类号： H01L21/761 , H01L21/265 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L21/8239 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108
摘要： PURPOSE:To provide a semiconductor device manufacturing method by which the narrow channel effect is suppressed and, at the same time, the substrate bias effect is also suppressed to a low level at the time of making elements finer. CONSTITUTION:Thick isolating oxide films are selectively formed on the surface of a silicon substrate 1 so as to isolate element forming areas from each other. Impurities are implanted into areas in the substrate by ion implantation through the thick isolating oxide films. As a result, retrograde wells 51 and 61 respectively having peak impurity concentration positions 51b and 61b are formed in the areas of the substrate 1 below the isolating oxide films. Then isolating oxide films 21 having greater thicknesses are formed by removing the upper parts of the isolating oxide films. Each film 21 has a reduced interelement isolation length L.

3. 发明专利

JPH0440865B2 失效
公开(公告)号：JPH0440865B2
公开(公告)日：1992-07-06
申请号：JP28820785
申请日：1985-12-20
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHIMANO HIROKI , SHIMIZU MASAHIRO , TSUKAMOTO KATSUHIRO , INUISHI MASAHIDE
IPC分类号： H01L27/10 , G11C11/34 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/08 , H01L29/10

4. 发明专利

JPH04142732A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04142732A
公开(公告)日：1992-05-15
申请号：JP26701590
申请日：1990-10-03
申请人： MITSUBISHI ELECTRIC CORP
发明人： YAMAGUCHI TAKEHISA , SHIMIZU MASAHIRO , TSUKAMOTO KATSUHIRO
IPC分类号： H01L29/78 , H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To avoid the increase in the leakage current in the case of inverse bias even if the upper part of a P-N junction is turned into silicide by a method wherein an impurity layer in inverse conductivity type to that of a semiconductor substrate formed by rotary oblique ion-implantation step. CONSTITUTION:In order to form an N diffused layer 7 by implanting an Si substrate 1 with As ions (a), the rotary oblique ion-implantation step (b) is applied. Through these procedures, since the junction interface 13 in the isolation impurity layers 5 is deeply formed, the distance between field oxide films 1 and edge parts (c) can be lengthened thus enabling the defects in the conventional device to be corrected. For example, the ion-implantation step is performed while rotating the Si substrate 1 in the oblique direction at the implantation angle of about 30-60 deg.C. In this step, about several scores of KeV-100KeV of implantion energy are expended while the effective dosage is 10 /cm. Meeting the requirements, the N diffused layer 7 is formed by performing diffusion step in a thermal diffusion furnace so as to form a P-N junction.

5. 发明专利

JPH03171672A MANUFACTURE OF MISFET 失效
公开(公告)号：JPH03171672A
公开(公告)日：1991-07-25
申请号：JP31126489
申请日：1989-11-29
申请人： MITSUBISHI ELECTRIC CORP
发明人： KOMORI SHIGEKI , KUSUNOKI SHIGERU , TSUKAMOTO KATSUHIRO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10
摘要： PURPOSE:To obtain a very small FET which is high in resistance to a punch-through phenomenon and operational speed by a method wherein impurity ions are implanted into a well region using a mask on the primary face of a substrate at such an energy level that the concentration peak of an impurity distribution is formed at a point deeper than the base of a source and a drain and a part of a channel layer is kept at a certain value or below in impurity concentration. CONSTITUTION:A thermal oxide film 2 and a nitride film pattern 3a are formed on a first conductivity type silicon substrate 1, and a field oxide film 2a is formed through thermal oxidation. Impurity ions are implanted with a high energy level to form a first high impurity concentration layer 5. Furthermore, impurity ions are implanted at a high energy level to form a second high impurity concentration layer 6 whose concentration is higher than that of the layer 5 under the layer 5. A channel doped layer 7 used for controlling the threshold of an FET is formed at a position shallower than the first high impurity concentration layer 5. A gate oxide film 13 is formed through thermal oxidation, and a conductor layer is deposed through a CVD method or a vacuum evaporation method, which is patterned into a gate electrode 8. By an ion implantation method, a second conductivity type source.drain region 10 is formed, and thus a fine MISFET is formed.

6. 发明专利

JPH033382B2 失效
公开(公告)号：JPH033382B2
公开(公告)日：1991-01-18
申请号：JP19470381
申请日：1981-11-30
申请人： MITSUBISHI ELECTRIC CORP
发明人： TSUKAMOTO KATSUHIRO , KOTANI HIDEO , YAKUSHIJI HISAO , HARADA HIROTSUGU , HIRATA KATSUHIRO
IPC分类号： H01L21/3213 , H01L21/3205

7. 发明专利

JPH02264464A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02264464A
公开(公告)日：1990-10-29
申请号：JP8595789
申请日：1989-04-05
申请人： MITSUBISHI ELECTRIC CORP
发明人： KOMORI SHIGEKI , TSUKAMOTO KATSUHIRO
IPC分类号： H01L27/092 , H01L21/265 , H01L21/8238
摘要： PURPOSE:To carry out the formation of a well and the implantation of channel ions using the same mask to lessen photoengraving processes in number, to implant impurity ions for the formation of the well with a prescribed energy so as to dispense with a thermal diffusion process, and to inject impurity of the same conductivity type with the well so as to prevent punch-through. CONSTITUTION:An SiO2 film 2 is provided to a P -Si substrate 1, and an Si3N4 mask 3 is deposited thereon through a resist 4. An isolating oxide film 3 is formed, and the mask 3 is removed. A resist mask 28 is deposited, and B ions are implanted. In this case, regions 29 are formed by the injection of B ions at a high energy and a P well 6 is formed at a low energy. The regions 29 serve as a channel stopper. Moreover, B ions are implanted into a channel 13 with a low energy to carry out the adjustment of a punch-through preventive Vth. Then, a resist mask 30 is coated, P ions are implanted properly choosing the implantation energy to form a region 31 and an N well 5, and B and As ions are implanted to form a channel layer 15 for the prevention of punch- through and for the adjustment of Vth. By this constitution, not only processes can be lessened in number but also a semiconductor device of this design can be reduced in production time.

8. 发明专利

JPH0249428A METHOD AND APPARATUS FOR FORMING THIN FILM ON SURFACE OF SEMICONDUCTOR SUBSTRATE 失效
公开(公告)号：JPH0249428A
公开(公告)日：1990-02-19
申请号：JP31581088
申请日：1988-12-13
申请人： MITSUBISHI ELECTRIC CORP
发明人： IWASAKI MASANOBU , ITO HIROMI , TOKUI AKIRA , MITSUI KATSUKICHI , TSUKAMOTO KATSUHIRO
IPC分类号： H01L21/302 , C23C14/34 , C23F4/00 , H01L21/304 , H01L21/3065 , H01L21/31
摘要： PURPOSE:To form a thin film of high quality on a clean surface by a method wherein a natural oxide film adhered on the surface of a semiconductor substrate is removed by a photochemical reaction under heating and thereafter, successively, a thin film is formed on the substrate surface without being exposed to the atmosphere in a chamber for thin film formation use. CONSTITUTION:HCl gas is introduced in a chamber 3 through an HCl gas introducing port 6 and the HCl gas is fed to the surface of an Si substrate 4. Then, a low-pressure mercury-arc lamp is lighted, whereby with ultraviolet light irradiated on the surface of the substrate 4 through an ultraviolet light incident window 2, the substrate 4 is heated at 200-700 deg.C. Whereupon, a natural oxide film adhered on the substrate 4 is removed by a synergistic effect of light and heat. Then, the HCl gas is exhausted through an exhaust vent 9. Then, a heating means 5a is actuated to heat the semiconductor substrate 4, gas for film formation use is introduced through a gas introducing port 36 for film formation use and a prescribed thin film is formed on the surface of the substrate 4.

9. 发明专利

JPS6438700A ION SOURCE 失效
公开(公告)号：JPS6438700A
公开(公告)日：1989-02-08
申请号：JP19416487
申请日：1987-08-03
申请人： MITSUBISHI ELECTRIC CORP
发明人： MORIMOTO HIROAKI , HOSONO KUNIHIRO , TSUKAMOTO KATSUHIRO , SASAKI YOSHINOBU
IPC分类号： G21G4/04 , G21K5/04 , H01L21/265
摘要： PURPOSE:To provide an ion source for producing a precisely controlled ion beam capable of forming a fine spot by using a substance of the same mass number which is obtained by separating a substance containing stable isotopes. CONSTITUTION:In regard to an ion source which produces an ion beam from an ionized substance, the substance which has only single mass number having a stable isotope is applied. For example, the alloy such as gold and antimony is applied. In this case only isotope preseparated Sb for antimony is applied. Thereby only a kind of isotope exists in the ion beam emitted and the isotope need not be separated. Therefore, the accuracy of working can be prevented from being lowered by being separated by the ion beam on the specimen every isotope even if normal electrical field and magnetic field orthogonal mass separator is applied.

10. 发明专利

JPS63211668A ONE-TRANSISTOR TYPE DYNAMIC MEMORY CELL 失效
公开(公告)号：JPS63211668A
公开(公告)日：1988-09-02
申请号：JP4427587
申请日：1987-02-26
申请人： MITSUBISHI ELECTRIC CORP
发明人： TSUKAMOTO KATSUHIRO
IPC分类号： H01L27/04 , G11C11/404 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/417
摘要： PURPOSE:To obtain a large memory capacitance with an extremely small area, by providing a second capacitance between first and second polysilicon electrodes on the top of the first polysilicon electrode and utilizing the first and second capacitances in parallel. CONSTITUTION:A first capacitor insulation film 4 is formed for example by forming a groove in a silicon substrate 11 and then oxidizing the bottom and side faces of the groove. A first memory capacitance MC1 is provided by a P region 21 and a first polycrystalline silicon electrode 22 formed on the opposite sides of the insulation film 4. Further, a second capacitor insulation film 24 is formed for example by oxidizing the surface of the first polysilicon electrode 22 and second memory capacitance MC2 is provided by the first polysilicon electrode 22 and a second polysilicon electrode 5 formed on the opposite sides of the second capacitor insulation film 24. This memory capacitance MC2 is stacked on the memory capacitance MC1. An epitaxial layer 100 is formed simultaneously with the formation of the first polysilicon electrode 22 serving as a memory terminal, and a read/write transistor is provided in the epitaxial layer 100. In this manner, the area occupied by a memory cell can be reduced substantially.

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