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1. 发明专利

JPS60235473A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60235473A
公开(公告)日：1985-11-22
申请号：JP9347284
申请日：1984-05-08
申请人： MITSUBISHI ELECTRIC CORP
发明人： KOUNO YOSHIO , YONEDA MASAHIRO , NAGATOMO MASAO
IPC分类号： H01L29/78 , H01L21/28 , H01L29/45 , H01L29/49
摘要： PURPOSE:To prevent a short circuit between a gate electrode and a source or a drain, and to enable high yield and high reliability by forming an insulating film on the side wall of gate polycrystalline silicon and obviating the silicifying of one part of the side wall of the gate polycrystalline silicon. CONSTITUTION:An isolation oxide film 2 is shaped to a P substrate 1, a gate oxide film 3 is formed, polycrystalline silicon is deposited and diffused, and a nitride film 9 is deposited. Gate polycrystalline silicon 5 is shaped, and arsenic is implanted. The side wall of the gate polycrystalline silicon 5 and source and drain regions are oxidized to form an oxide film 10. The nitride film 9 is removed, a high melting-point metal is evaporated, a metallic silicide layer 6 is shaped, and excess platinum is removed. A phospho-silicate glass layer 7 is deposited, an AlSi wiring layer 8 is evaporated, a wiring pattern is formed, the AlSi wiring layer 8 is etched, and TiW is removed, thus completing an MOS type semiconductor device. A short circuit between a gate electrode and a source or a drain is prevented, and high yield is obtained.

2. 发明专利

JPS5779621A Plasma processing device 失效
标题翻译：等离子体加工装置
公开(公告)号：JPS5779621A
公开(公告)日：1982-05-18
申请号：JP15608680
申请日：1980-11-05
申请人： Mitsubishi Electric Corp
发明人： ABE HARUHIKO , HARADA HIROJI , DENDA MASAHIKO , NAGASAWA KOUICHI , KOUNO YOSHIO
IPC分类号： H01L21/31 , C23C8/36 , C23C16/513 , C23F1/00 , C23F4/00 , H01J37/32 , H01L21/205 , H01L21/302 , H01L21/3065
CPC分类号： H01J37/32623 , C23C8/36 , C23C16/513 , C23F1/00 , C23F4/00 , H01J37/32357 , H01J37/32678 , H01L21/302
摘要： PURPOSE: To enable generating of a plasma current along a reaction vessel, by a method wherein a static magnetic field, being uneven in an axial direction, is generated in the plasma reaction vessel using an air-core coil, and a high-frequency magnetic field, being uneven in an axial direction, is added further through a high-frequency waveguide.
CONSTITUTION: An air-core coil 1, generating a static magnetic field being uneven in an axial direction, and a high-frequency guidewave 2, producing a high- frequency magnetic field uneven in an axial direction, are mounted around a plasma generating glass tube 3 to constitute a plasma generating part A. If the high-frequency guidwave 2 generates a magnetic field having a magnetic field satisfying a cyclone resonance condition of an electron, an electron in the glass tube 3 is accelerated, and a plasma so produced is fed to a magnetic field through the polarization of the electron to produce a plasma current flowing along the glass tube 3 and to flow out to a plasma reaction part B. The plasma is shaped using coils 14 and 15, and a substrate 10, placed on a stand 9, is irradiated with the plasma so shaped.
COPYRIGHT: (C)1982,JPO&Japio
摘要翻译：目的：为了能够沿着反应容器产生等离子体电流，通过使用空心线圈的等离子体反应容器中产生在轴向上不均匀的静磁场和高频磁铁的方法通过高频波导进一步添加在轴向不均匀的场。构成：产生轴向不均匀的静磁场的空心线圈1和产生轴向不均匀的高频磁场的高频导波2安装在等离子体发生玻璃管的周围构成等离子体产生部件A.如果高频引导波2产生具有满足电子的旋风共振条件的磁场的磁场，则玻璃管3中的电子被加速，并且将如此产生的等离子体馈送通过电子的偏振到磁场，产生沿着玻璃管3流动的等离子体电流并流出到等离子体反应部分B.等离子体使用线圈14和15成形，并且将基板10放置在立柱9被等离子体照射成形。

3. 发明专利

JPS60225447A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60225447A
公开(公告)日：1985-11-09
申请号：JP8227584
申请日：1984-04-23
申请人： MITSUBISHI ELECTRIC CORP
发明人： YONEDA MASAHIRO , KOUNO YOSHIO , NAGATOMO MASAO
IPC分类号： H01L21/768 , H01L21/28 , H01L21/283 , H01L23/522
摘要： PURPOSE:To improve the insulation by inbiting the generation of hillocks from an aluminum wiring film by a method wherein a plasma polymer film is formed as the interlayer insulation film, and the first layer aluminum wiring film is connected to the second layer aluminum wiring film by forming a contact hole in this plasma polymer film. CONSTITUTION:After formation of the first layer aluminum wiring film 7, the plasma polymer film 10 is formed in the part other than the through-hole region by using the technique of plasma deposition. An Si oxide film 8 as the interlayer insulation film is formed on the plasma polymer film 10, and the first layer aluminum wiring film 7 and the second layer aluminum wiring film 9 are formed thereon. Since the polymer film 10 can be formed at a temperature extremely close to room temperature and is stable in characteristics, this film can perfectly inhibit the hillock and the like from the first layer aluminum wiring film 7 and serves as a stable interlayer insulation film.

4. 发明专利

JPS5834959A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS5834959A
公开(公告)日：1983-03-01
申请号：JP13486681
申请日：1981-08-25
申请人： MITSUBISHI ELECTRIC CORP
发明人： KOUNO YOSHIO , ASAI SOTOHISA
IPC分类号： H01L27/08 , H01L21/322 , H01L27/092 , H01L29/78
摘要： PURPOSE:To enable a high speed operation, by forming a C FET on a semiconductor substrate constituted of a non-defect layer formed from the surface of the semiconductor substrate to the neighborhood of a well depth and a crystal defect layer formed in the substrate. CONSTITUTION:A CZ substrate is applied to an appropriate low temperature heat treatment, and thus a substrate containing crystal defect nuclei is obtained. When this substrate is heat-treated at a high temperature, oxygen out-diffuses in the neighborhood of the substrate, nuclei are crushed, and thus the non-defect layer 10a is obtained. Nuclei grow in this substrate, and the crystal defect layer 10b is formed. The width of the non-defect layer 10a can be controlled by a heat treatment method and is formed normally to the same degree as the depth of an N type well 2 diffused layer. Then, a C FET is formed on this substrate 10. Thus, a latch-up is not generated, and the formation of fine patterns or a high speed operation is enabled.

5. 发明专利

JPS60225475A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60225475A
公开(公告)日：1985-11-09
申请号：JP8227484
申请日：1984-04-23
申请人： MITSUBISHI ELECTRIC CORP
发明人： YONEDA MASAHIRO , NAGATOMO MASAO , KOUNO YOSHIO
IPC分类号： H01L29/78 , H01L21/28 , H01L29/43 , H01L29/49
摘要： PURPOSE:To enable the reduction in resistance of a gate and a wiring by a method wherein a silicide film of high melting point metal is formed on a polycrystalline Si film for the gate and the wiring, and further a film of high melting point metal is formed on the silicide film, resulting in a three-layer structure. CONSTITUTION:After a field oxide film 2 for element isolation is formed on an semiconductor substrate 1, a gate oxide film 3 is formed by thermal oxation. Next, a buried contact hole is bored in a required part of the gate oxide film 3, a polycrystalline Si layer doped with arsenic is formed over the whole surface, which is then patterned, thus forming a polycrystalline Si film 4 for the gate and the wiring selectively on the gate oxide film 3. Heat treatment is carried out so that the silicide film 6 of a high melting point metal such as Mo, Ti, Ta or the like may be formed on the Si film 4. Further, a high melting point metal film 7 is formed on said silicide film 6, and the gate and the wiring are formed by etching.

6. 发明专利

JPS5843559A COMPLEMENTARY SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5843559A
公开(公告)日：1983-03-14
申请号：JP14198381
申请日：1981-09-08
申请人： MITSUBISHI ELECTRIC CORP
发明人： ASAI SOTOHISA , KOUNO YOSHIO
IPC分类号： H01L27/08 , H01L27/092 , H01L29/78
摘要： PURPOSE:To raise the integration density by suppressing latch-up through deepened junction of the diffusion layers for ohmic contact of the power source terminal to the substrate and well layer and by eliminating necessity of making large the interval between the source and drain of MIS FET formed on the substrate and well. CONSTITUTION:Latch-up can be suppressed because the base resistance R1 of lateral P-N-P transistor Tr1 and the base resistance R3 of vertical N-P-N transistor Tr2 can be reduced by deepening the junction of the N diffusion layer 32 and P diffusion layer 21 for the ohmic contact. When R1 is reduced, the base voltage of Tr1 is more stabilized and when R3 is reduced, the base voltage of Tr2 is stabilized and thereby generation of positive feedback loop can be suppressed. When any one of the base resistances R1 and R2 is reduced, a resultant suppression effect can be obtained.

7. 发明专利

JPS57109367A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS57109367A
公开(公告)日：1982-07-07
申请号：JP18880280
申请日：1980-12-25
申请人： MITSUBISHI ELECTRIC CORP
发明人： KOUNO YOSHIO , HARADA KOUJI , DENDA MASAHIKO , NAGASAWA KOUICHI , ABE HARUHIKO
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/417 , H01L29/47 , H01L29/78 , H01L29/872
摘要： PURPOSE:To make possible high integration of memory cells on the same substrate surface by providing MOSFET three-dimentionally at the top of a memory capacitor. CONSTITUTION:An isolation oxide film 12, an N type active region 13 and a gate oxide film 14 are formed on a P type silicon semiconductor substrate 11. Then a film 14 on the region 13 is removed by etching and an N type epitaxial layer 15 is formed on the region 13 and a poly silicon layer 16 is formed on the film 12, 14. Platinum is vapored on the entire surface and then a Schottky barrier is formed by making the layer 16 Pt Si. An oxide film 17 is formed by treating the layer 16 and an N type polysilicon layer 18 is grown. The layer 18 is removed except a portion on the layer 15. Windows for taking out electrodes are made after forming an oxide film 17. Aluminum electrodes 19, 20 are made at the windows.

8. 发明专利

JPS5769772A Semiconductor memory unit 失效
标题翻译：半导体存储单元
公开(公告)号：JPS5769772A
公开(公告)日：1982-04-28
申请号：JP14548180
申请日：1980-10-16
申请人： Mitsubishi Electric Corp
发明人： NAGASAWA KOUICHI , HARADA HIROJI , DENDA MASAHIKO , ABE HARUHIKO , KOUNO YOSHIO
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10805
摘要： PURPOSE: To enhance density of integration and to obtain a dynamic random access memory unit contriving enlargement of capacity thereof by a method wherein respecitve parts of the unit are disposed solidly.
CONSTITUTION: A field insulating film 12 and an n
+ type diffusion region 13 are formed on a p type silicon semiconductor substrate 11. The n
+ type diffusion region 13 constitutes a capacitor between the semiconductor substrate 11. A p
+ type vapor growth layer 14 is formed selectively on the n
+ type diffusion region 13, and moreover a transfer gate electrode 15 consisting of polycrystalline silicon to be connected to a word line 18 through a gate insulating film 19 is formed, and an n
+ type vapor growth layer 16 to be connected to a bit line 17 is formed on the p
+ type vapor growth layer 14. Because the transfer transistor being length of the gate electrode thereof decided by thickness of polycrystalline silicon is constituted in the vertical direction, and the transistor and the capacitor are integrated solidly, density of integration is enhanced.
COPYRIGHT: (C)1982,JPO&Japio
摘要翻译：目的：提高一体化的密度，并获得动态随机存取存储器单元，通过其中单元的重新分配部分牢固地设置的方法来扩大容量。构成：在p型硅半导体衬底11上形成场绝缘膜12和n +型扩散区13.n +型扩散区13构成半导体衬底11之间的电容器.P + 形成n +型扩散区域13，并且形成由多晶硅构成的转移栅电极15，该多晶硅通过栅极绝缘膜19与字线18连接，n型在p +型蒸气生长层14上形成与位线17连接的+ +型蒸气生长层16.由于以多晶硅厚度决定的栅电极的长度的传输晶体管是以垂直方向，晶体管和电容器整体积分，增强了集成度。

9. 发明专利

JPS615568A MANUFACTURE OF COMPLEMENTARY MOS INTEGRATED CIRCUIT 失效
公开(公告)号：JPS615568A
公开(公告)日：1986-01-11
申请号：JP10493184
申请日：1984-05-22
申请人： MITSUBISHI ELECTRIC CORP
发明人： KOUNO YOSHIO
IPC分类号： H01L27/08 , H01L21/324 , H01L21/8238 , H01L27/092
摘要： PURPOSE:To greatly improve the latchup-withstanding capability by a method wherein an N substrate containing a high concentration of oxygen is exposed to a high temperature for the diffusion outward of the contained oxygen and another stage of heat treatment follows for the generation of oxygen donors. CONSTITUTION:When an N substrate 1 containing a high concentration of oxygen is exposed to a high temperature, of 1,150 deg.C for example, the contained oxygen is diffused outward and, when the substrate 1 is exposed to 450 deg.C for dozens of hours, oxygen donors are created. Few oxygen donors are created on the surface of the substrate 1 where oxygen is low in concentration. Oxygen is caused to be diffused outward before the formation of a P well 2. Conventional MOS- producing steps are followed, which terminate when metal is vapor-deposited for an electrode wiring 8. After the lower-temperature heat treatment for the creation of oxygen donors, the electrode wiring 8 is completed. In this design, for the same reason as the formation of an N epitaxial layer on the N substrate 1, the latchup-withstanding capability is enhanced.

10. 发明专利

JPS60225448A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60225448A
公开(公告)日：1985-11-09
申请号：JP8227684
申请日：1984-04-23
申请人： MITSUBISHI ELECTRIC CORP
发明人： KOUNO YOSHIO , YONEDA MASAHIRO , NAGATOMO MASAO
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/88
摘要： PURPOSE:To contrive to remove interlayer short by a method wherein a hillock is formed by heat-treating the lower metal formed on a substrate, and is selectively removed by sputter etching; then, a structure of multilayer wiring is formed. CONSTITUTION:The lower metal 2 on the substrate 1 is patterned, and then a heat treatment generating the hillock 6 is carried out. When sputter-etched with a chlorine series gas, the hillock 6 a projection is etched more rapidly than the other metal. An interlayer insulation metal 3 is formed by the CVD method. Since its temperature is set lower than the heat-treating temperature, the hillock 6 does not grow therewith. The interlayer insulation film 3 is etched by patterning a through-hole 4 by lithography, and the upper metal is formed, resulting in the construction of a multilayer wiring without interlayer short.

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