专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2012146832A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012146832A
公开(公告)日：2012-08-02
申请号：JP2011004488
申请日：2011-01-13
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： YUYA NAOKI , WATANABE AKIHIRO , NAKAO YUKIYASU , WATABE KIYOTO
IPC分类号： H01L29/872 , H01L29/06 , H01L29/47
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a termination structure capable of enduring withstand voltage in a high electric field and capable of suppressing dielectric breakdown.SOLUTION: A semiconductor device according to the present invention comprises: a recess structure 3 formed on a surface of a drift region 2 so as to surround an SBD electrode 5 in a plan view; a guard ring injection layer 4 that is formed in the bottom surface of the recess structure 3 and is connected to the SBD electrode 5; a protective film 7 formed along the recess structure 3 so as to cover at least the recess structure 3; and a semi-insulating film 20 formed on the protective film 7 along the protective film 7. The semi-insulating film 20 has a connection portion 21 connected to the SBD electrode 5 inside the region surrounded by the recess structure 3, and a connection portion 22 connected to the drift region 2 outside the region surrounded by the recess structure 3.
摘要翻译：要解决的问题：提供一种具有能够在高电场中耐受耐受电压并能够抑制电介质击穿的端接结构的半导体器件。解决方案：根据本发明的半导体器件包括：在俯视图中围绕SBD电极5形成在漂移区域2的表面上的凹陷结构3; 保护环注入层4，形成在凹部结构体3的底面，与SBD电极5连接; 沿着凹部结构3形成的保护膜7，以至少覆盖凹部结构3; 以及沿着保护膜7形成在保护膜7上的半绝缘膜20.半绝缘膜20具有连接部分21，该连接部分21在由凹陷结构3包围的区域内连接到SBD电极5，连接部分 22连接到由凹槽结构3包围的区域之外的漂移区域2.版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2003324937A Driving apparatus 审中-公开
标题翻译：驱动装置
公开(公告)号：JP2003324937A
公开(公告)日：2003-11-14
申请号：JP2002133960
申请日：2002-05-09
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： WATABE KIYOTO
IPC分类号： H02M1/08 , H02M7/48 , H03K17/06 , H03K17/16 , H03K17/567 , H03K17/687
CPC分类号： H03K17/063 , H02M7/538 , H03K17/168 , H03K17/567 , H03K17/6871
摘要： PROBLEM TO BE SOLVED: To provide a driving apparatus which can prevent a mistake operation when the potentials of connecting nodes of two switching devices connected in a totem pole manner are changed, and which can reduce a power consumption. SOLUTION: A dummy circuit 303 fundamentally has a constitution similar to that of level shifting circuits 203a, 203b, and an HVNMOS 311 is always set to a non-conducting state. A mask circuit 403 removes a noise in signals S200a, S200b from the circuits 203a, 203b by utilizing a signal S300 from the circuit 303. Control signals S100a, S100b include repeating pulses, which are transmitted to the S input and the R input of an RS flip-flop 502. PMOSes 215, 225 set current paths 210, 220 to non-conducting states based on the output signal S500 of the flip-flop 502, and thereby suitably pauses one of the circuits 203a, 203b. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种驱动装置，其能够防止当以图腾的方式连接的两个开关装置的连接节点的电位变化时的错误操作，并且这可以降低功耗。解决方案：虚拟电路303基本上具有类似于电平移位电路203a，203b的结构，并且HVNMOS 311总是设置为非导通状态。掩模电路403通过利用来自电路303的信号S300从电路203a，203b除去信号S200a，S200b中的噪声。控制信号S100a，S100b包括发送到S输入端的重复脉冲和发送到S输入端的R输入端 RS触发器502. PMOS 215,225基于触发器502的输出信号S500将电流路径210,220设定为非导通状态，从而适当地暂停电路203a，203b之一。版权所有（C）2004，JPO

3. 发明专利

JPH11297815A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11297815A
公开(公告)日：1999-10-29
申请号：JP9746098
申请日：1998-04-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： AKIYAMA HAJIME , WATABE KIYOTO , YAMAWAKI MASAO , YASUDA NAOKI , YAMAMOTO SHIGEYUKI
IPC分类号： H01L21/762 , H01L21/76 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To make it possible to achieve simultaneously a reduction in the stress of a semiconductor device, a flattening of a BPSG layer and the simplification of the production process of the semiconductor device in the formation of trenches. SOLUTION: Diffused layers 23 and 26 and a field oxide film 2 are formed in and on a substrate 20 and thereafter, trenches 6 are formed in the substrate 20. The trenches 6 are formed in such a way as to avoid the film 2. The trenches 6 are filled with an oxide film 7, which is an insulator film, and a BPSG layer 8. At the time of the filling, an etch-back of the film 7 and the layer 8 is not performed.

4. 发明专利

JPH09120995A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH09120995A
公开(公告)日：1997-05-06
申请号：JP5935696
申请日：1996-03-15
申请人： MITSUBISHI ELECTRIC CORP
发明人： WATABE KIYOTO , TERAJIMA TOMOHIDE
IPC分类号： H01L21/76 , H01L21/8234 , H01L27/088 , H01L27/12 , H01L29/10 , H01L29/739 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is excellent in drive performance and suitable for high integration. SOLUTION: A high resistance n-type base layer 5 is formed on a silicon substrate 1 with an insulation layer formed of silicon oxide film in between. A p-chMOS transistor 30 is formed in the layer 5. The transistor 30 is electrically separated from other elements thanks to trench separation of a groove 63. The p type source layer 9 in the transistor 30 is formed in a manner to surround a p type drain layer 11 elliptically and flatly.

5. 发明专利

JPS63187623A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63187623A
公开(公告)日：1988-08-03
申请号：JP1943687
申请日：1987-01-29
申请人： MITSUBISHI ELECTRIC CORP
发明人： YASUE TAKAO , WATABE KIYOTO
IPC分类号： H01L21/3205 , H01L21/285
摘要： PURPOSE:To improve the coverage of interconnection in a contact hole, by applying metal ions to side walls of the contact hole on which the interconnection layer is deposited in a smaller thickness, by means of the convergent ions beam technique. CONSTITUTION:An upper interconnection layer 3 is formed on a silicon substrate 1 through an interlayer insulation film 2 having a contact hole 5. The interconnection layer 3 has thin sections on the side walls of the contact hole 5; ion beam 4 is applied to these thin sections by means of the convergent ion beam technique so that the material of the interconnection layer is selectively deposited on the thin sections so as to increase the thickness thereof. In this manner, the coverage of interconnection in a contact hole can be improved.

6. 发明专利

JPS6386453A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6386453A
公开(公告)日：1988-04-16
申请号：JP23205386
申请日：1986-09-29
申请人： MITSUBISHI ELECTRIC CORP
发明人： KOTANI HIDEO , OKAMOTO TATSURO , ONO TAKIO , WATABE KIYOTO , KINOSHITA YASUSHI , NISHIKAWA KIICHI
IPC分类号： H01L21/3205
摘要： PURPOSE:To make larger the width of a first conductor film than the width of a wiring even though side etchings are generated and to improve the coverage forms of the step parts of an insulating film by a method wherein the first conductor film is etched using the wiring and parts of the thin films left only on the sidewall parts of this wiring as masks. CONSTITUTION:A thin film 10 consisting of an Si oxide film, a titanium-tungsten alloy film or the like is formed on the surface of a barrier metal film 2 and the surface of a wiring 3 by a CVD method or the like. Then, the thin film 10 is anisotropically etched by a reactive ion etching method or the like and thin films 10a and 10b are left only on the sidewall parts of the wiring 3. Then, the barrier metal film 2 is etched using the wiring 3 and the thin films 10a and 10b as masks to form a barrier metal film 21. At this time, the amounts of side etchings 50a and 50b to be generated are each contrived so as to become smaller than the widths of the bottom surfaces of the thin films 10a and 10b. Then, the thin films 10a and 10b are removed by isotropically etching. As the width of the barrier metal film 21 is larger than that of the wiring 3, the coverage form of an insulating film 60 to be lastly formed is improved.

7. 发明专利

JPS62123715A FORMATION OF CONTACT ELECTRODE 失效
公开(公告)号：JPS62123715A
公开(公告)日：1987-06-05
申请号：JP26351085
申请日：1985-11-22
申请人： MITSUBISHI ELECTRIC CORP
发明人： MATSUDA SHUICHI , ARIMA HIDEAKI , WATABE KIYOTO , YAMANO TAKESHI
IPC分类号： H01L21/28 , H01L21/288
摘要： PURPOSE:To properly execute the embedding of the contact hole formed in the insulating film on the Si substrate, to flatly form the surface of the titled contact electrode and to prevent the disconnection of the wiring by a method wherein the contact hole is filled with a metal layer generating no alloy spike by a plating method in the interface between the Si substrate and the wiring layer. CONSTITUTION:An oxide film 2 is formed on a substrate 1 and a photo resist film 5 is coat-formed thereon. A dry etching is performed on the insulating film 2 with a CHF3 plasma to form a contact hole 3. An Ag layer 6 is precipitated in the hole 3 by plating in a thickness equal to that of the insulating film 2. Lastly, an Al or AlSi alloy layer is formed thereon by a sputtering method and a mask of the desired wiring pattern is formed thereon using the photo resist. A dry etching is performed through the mask to obtain an Al or AlSi alloy wiring layer 4. Thus, the embedding of the contact hole is properly executed, the surface of this contact electrode is flatly formed and the disconnection of the wiring is prevented.

8. 发明专利

JPS61278166A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61278166A
公开(公告)日：1986-12-09
申请号：JP12009285
申请日：1985-06-03
申请人： MITSUBISHI ELECTRIC CORP
发明人： WATABE KIYOTO
IPC分类号： H01L29/78 , H01L21/265
摘要： PURPOSE:To enable the reduction of the transconductance to be prevented and to enable the sheet resistance of the source-drain to be reduced by changing a desired region of the gate electrode or of the electrode and the source-drain into silicide. CONSTITUTION:A region 30 is the silicide region of the gate electrode when heat treatment is applied. A gate electrode 20 comprising a gate insulating film 2 and a polycrystalline silicon 3 is formed on a silicon substrate 1, and then with the gate electrode as a mask, e.g., P is ion-implanted, forming a low density N-type region 4. Next, e.g., platinum 21 is deposited on the silicon substrate 1, and then heat treatment is applied, changing only the polycrystalline silicon 3 into silicide. Then, the remaining platinum 21 and the gate insulating film 2 are removed, thereafter with the silicide region 30 of the gate electrode as a mask As ions are implanted, and heat treatment is applied to form a high density N-type region 5, achieving a LDD structure. Finally, a contact window is opened in the high density N-type region 5, and the electrode wiring is performed, completing the device.

9. 发明专利

JPS61278165A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61278165A
公开(公告)日：1986-12-09
申请号：JP11913785
申请日：1985-05-31
申请人： MITSUBISHI ELECTRIC CORP
发明人： WATABE KIYOTO
IPC分类号： H01L29/78 , H01L21/265
摘要： PURPOSE:To easily implement a shallow junction by adding a process of making a low density n-type region amorphous by implanting thereinto silicon ions or inert gas ions, thereby causing the crystallizability to be recovered by rapid annealing or low-temperature annealing. CONSTITUTION:A gate electrode comprising a gate oxide film 2 and a polycrystalline silicon 3 is formed on a p-type silicon substrate 1, the then with the gate electrode as a mask, for instance, P ions are implanted, forming a low dinsity n-type region 4 amorphous 21, and subsequently an oxide film 9 is deposited by LPCVD. Further, the oxide film 9 is left only on the side walls of the gate by anisotropic etching, and thereafter with the gate electrode 20 and the oxide films 10 on the gate side walls as a mask, for instance, As ions are implanted to form a high density n-type region 5, forming a LDD structure. Thereafter, the source and drain regions are activated by low temperature annealing such as rapid annealing, and the processes such as the opening of a contact window and the electrode wiring are performed.

10. 发明专利

JPS61201471A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61201471A
公开(公告)日：1986-09-06
申请号：JP4395185
申请日：1985-03-04
申请人： MITSUBISHI ELECTRIC CORP
发明人： WATABE KIYOTO , KUSUNOKI SHIGERU
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78
摘要： PURPOSE:To facilitate a process for forming impurity regions in a source and a drain by easily controlling the width of an oxide film shaped to a gate side- wall section. CONSTITUTION:A gate insulating film 12 and a polycrystalline silicon film 13 as a gate electrode are formed onto a P-type silicon substrate 11, a nitride film 14 is deposited, and a gate is shaped through photoetching. An oxide film 15 is formed to a gate side-wall section through heat treatment while using the nitride film 14 as a mask. Arsenic ions III are implanted while employing the nitride film 14 and the oxide film 15 as masks to shape high-concentration regions 16 in a source and a drain. The nitride film 14 and 15 are removed, and phosphorus ions IV are implanted to form low-concentration regions 17 in the source and the drain, thus acquiring LDD structure.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式