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1. 发明专利

JP2001202817A PLANE TYPE DISPLAY APPARATUS 失效
公开(公告)号：JP2001202817A
公开(公告)日：2001-07-27
申请号：JP2000009716
申请日：2000-01-19
申请人： ADVANCED DISPLAY KK , MITSUBISHI ELECTRIC CORP
发明人： OGAWA IKUO , YANAI SHIGERU , NISHIDA YOSHIHIDE , ITO ATSUSHI , YONEDA TOSHIYUKI
IPC分类号： G09F9/00 , F21V8/00 , F21Y103/00 , G02F1/13 , G02F1/1335 , G02F1/13357
摘要： PROBLEM TO BE SOLVED: To obtain a plane type display apparatus capable of securing a space for an electrical circuit required for driving the display apparatus without degrading an optical capability (brightness and brightness evenness) of a surface light source apparatus in an edge light manner used in a back light, in a thin plane type display apparatus having a permeating type of display panel. SOLUTION: In a light guiding plate 3 constituting a surface light source apparatus in a edge light manner, a luminous surface is a plane and its rear surface is constituted by a slanted plane part 31 in which a thickness of the light guiding plate 3 is linearly reduced by directing from a light entering part getting light from a linear light source 1 toward an anti-light entering part and a parallel plane part 32 in parallel with a luminous surface in the vicinity of the anti-light entering part. Border parts of two surfaces adjacent are connected to each other by using a curved surface of the border part in which the two surfaces adjacent becomes a connecting surface and at the same time, reflecting dots are formed on the rear surface side of the light guiding plate 3 with a predetermined shape and density.

2. 发明专利

JPH0682829B2 失效
公开(公告)号：JPH0682829B2
公开(公告)日：1994-10-19
申请号：JP31159692
申请日：1992-11-20
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKAMOTO TATSURO , OGAWA IKUO
IPC分类号： H01L29/43 , H01L21/28 , H01L21/3205 , H01L23/52 , H01L29/46

3. 发明专利

JPH05198790A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05198790A
公开(公告)日：1993-08-06
申请号：JP31159792
申请日：1992-11-20
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKAMOTO TATSURO , OGAWA IKUO
IPC分类号： H01L29/43 , H01L21/28
摘要： PURPOSE:To prevent a deposition of silicon, which is generated between a silicon layer and a second metallic film for wiring, by forming a first metallic film as a barrier metal, and thereafter, by forming thereon the second metallic film for wiring. CONSTITUTION:A silicon oxide film is formed on the principal surface of a silicon substrate 1. After forming thereon a silicon oxide film BPSG4 including boron and phosphorus, a contact hole 7 is formed. Then, by injecting ions, an impurity diffusion layer is formed near the surface of the silicon substrate 1. Subsequently, a first metallic film 5 is formed. As the metal of the film 5, the one to give an effective diffusion barrier between aluminum and silicon is selected. Finally, a second metallic film is formed out of such a metal as aluminum including silicon, and the metallic film is sintered by a heat treatment. Owing to boron included in the insulation film BPSG4, the diffusion of silicon into the second metallic film formed out of aluminum including silicon is prevented. Thereby, the deposition of silicon onto the interface between the silicon substrate and a metallic electrode, which is caused by a solid phase epitaxial growth of silicon, can be prevented.

4. 发明专利

JPH02168626A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH02168626A
公开(公告)日：1990-06-28
申请号：JP16757789
申请日：1989-06-29
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKUMURA YOSHIKI , NAGATOMO MASAO , OGAWA IKUO , MATSUKAWA TAKAYUKI , GENJIYOU HIDEKI , HACHISUGA ATSUSHI
IPC分类号： H01L23/52 , H01L21/3205
摘要： PURPOSE:To obtain a highly reliable wiring structure excellent in electric conduction by constituting at least one out of a plurality of wiring layers as a structure wherein a barrier metal layer, an aluminum alloy layer, and an antireflection film are laminated in said order from a semiconductor substrate side. CONSTITUTION:An auxiliary word line 12a is connected with a lower layer word line 10a, on a specified field oxide film 22. The auxiliary word line 12a is constituted as a three layer lamination structure wherein a barrier metal layer 6, an aluminum alloy layer 7, and an anti reflection film 8 are stacked in order from the lower layer. At the contact part between the auxiliary word line 12a and the word line 10a, the auxiliary word line 12a is constituted as a four layer structure wherein a silicide layer 20, a barrier metal layer 6, an aluminum alloy layer 7 and an antireflection film 8 are stacked in order from the lower layer. In this case, the antireflection film 8 prevents exposure light from scattering at the time of patterning the wiring layer, thereby realizing the microstructure of the wiring pattern. The barrier metal layer 6 at the contact part improve contact characteristics. By this set-up, the reliability of the wiring layer is improved.

5. 发明专利

JPH02117152A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02117152A
公开(公告)日：1990-05-01
申请号：JP27120288
申请日：1988-10-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： WAKAMIYA WATARU , OKUMURA YOSHIKI , OGAWA IKUO , OZAKI KOJI , MATSUKAWA TAKAYUKI , NAGATOMO MASAO
IPC分类号： H01L21/302 , H01L21/28 , H01L21/3065 , H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To contrive a proper etching process by etching insulating film by the use of a mask corresponding to the depth of a contact hole. CONSTITUTION:A photomask 11a is provided on the upper side of a resist 13a and only a place of opening 12a is formed on the photomask and its opening corresponds to a contact hole. Once irradiating, an opening 14a is formed. Then the contact hole is formed by etching an insulating film 10 that is exposed to the opening 14a with a RIE process. Then, after removing the resist 13a, a resist 13b is applied newly. A photomask 11b is provided and an opening 12b is formed at a position corresponding to the contact hole. Further, an opening 14b is formed with irradiation. Then a contact hole T1 is formed by etching. Even if etching thicknesses of the insulating film 10 are different, etching time in response to the thickness is secured. Consequently, no overetching, insufficient etching and the like take place in this manufacturing process.

6. 发明专利

JPH0279467A SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0279467A
公开(公告)日：1990-03-20
申请号：JP23081388
申请日：1988-09-14
申请人： MITSUBISHI ELECTRIC CORP
发明人： GENJIYOU HIDEKI , MATSUKAWA TAKAYUKI , NAGATOMO MASAO , OGAWA IKUO , OKUMURA YOSHIKI , HACHISUGA ATSUSHI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108
摘要： PURPOSE:To prevent influx of electric charges generated by alpha-beam into a memory cell in better performance by including high concentration impurities in a first electroconductive type impurity layer, which is to become a barrier layer, and forming a certain distance apart from the boundary of a second electroconductive type impurity region constituting a memory element. CONSTITUTION:The impurity concentration of a P -buried layer 40 concerned to work as a barrier layer is controlled to 10 -10 cm , with a concentration slope of 10-10 cm continued to the region of P-type well layer having an impurity concentration of 10 cm . This P -buried-layer 40 is situated 1.0-2.0mum apart from the surface of silicon base board, with peak value of the impurity concentration lying preferably apart 1.5mum in the order of magnitude 10 cm . When alpha-beam is incident on the P-type well layer 2 as a memory forming region where P -buried layer 40 with controlled impurity concentration and position of forming, most of electron-positive hole couples produced in the silicon base board by irradiation of alpha-beam are hindered by the P -buried layer 40. This precludes influx into N-type impurity dispersive regions 61, 62, which constitute memory cell.

7. 发明专利

JPH0279466A MANUFACTURE OF SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0279466A
公开(公告)日：1990-03-20
申请号：JP23081688
申请日：1988-09-14
申请人： MITSUBISHI ELECTRIC CORP
发明人： GENJIYOU HIDEKI , OGAWA IKUO , MATSUKAWA TAKAYUKI , NAGATOMO MASAO , OKUMURA YOSHIKI , HACHISUGA ATSUSHI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To prevent generation of residues in the boundary region between well layers by performing removal so that the main surface of a first semiconductor region is exposed in the condition trench is filled with a filling material, when the trench formed in the first semiconductor region is to be filled with filler, and then removing the remaining filling material in the condition that trench part and the exposed main surface of the first semiconductor region are masked. CONSTITUTION:An embedded deposit layer 16a formed over the whole surface of a silicon base board is removed by means of etching-back until the deposit layer fills only the trench concerned and keeps the same level as the surface of the region of P-type well layer 2. In this etching process, resist film 14 is formed selectively only on the region of P-type well layer 2 where trench is formed. Further, etching of the embedded deposit layer 16a is conducted using this resist film as a mask. Accordingly only trenches in the deposit layer 16a are filled, and an embedded separate layer 16 is accomplished. At this time, no residues of embedded deposit layer 16a are produced at level difference part formed between P-type and N-type well layers 2, 3.

8. 发明专利

JPH01147843A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01147843A
公开(公告)日：1989-06-09
申请号：JP30805887
申请日：1987-12-03
申请人： MITSUBISHI ELECTRIC CORP
发明人： OZAKI KOJI , OGAWA IKUO , OKUMURA YOSHIKI , NAGATOMO MASAO , WAKAMIYA WATARU
IPC分类号： H01L21/3205 , H01L21/822 , H01L23/522 , H01L23/532 , H01L27/04 , H01L27/108
摘要： PURPOSE:To provide good uniformity of the thickness of wirings and to wire with high reliability by depositing polysilicon on a contact, burying it by etching back, and wiring with a second conductive material. CONSTITUTION:After an interlayer insulating film 4 is patterned, a first conductive film 5 is initially deposited. The film 4 is etched back to the position indicated by the film 5. A diffused layer of a substrate is not exposed on the surface at all by the etching-back. A second conductive material 6 is deposited, and patterned. Then, the film 5 is ohmically connected to the material 6. Thus, good uniformity of the thickness of wirings is obtained, the disconnection trouble ratio due to the migration of the wirings is reduced, and wirings of high reliability is performed.

9. 发明专利

JPH01123416A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01123416A
公开(公告)日：1989-05-16
申请号：JP28162287
申请日：1987-11-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： NAGATOMO MASAO , MATSUKAWA TAKAYUKI , OZAKI KOJI , WAKAMIYA WATARU , OKUMURA YOSHIKI , OGAWA IKUO
IPC分类号： H01L21/22 , H01L21/8238 , H01L27/08 , H01L27/092
摘要： PURPOSE:To form two semiconductor layers having mutually opposite conductivity type active regions without overlapping, by performing doping with impurities when a plurality of semiconductor layers are formed in region, which is at a specified distance from a boundary line between the intended two semiconductor layers. CONSTITUTION:An oxide film 2 and a nitride film 3 are sequentially formed on a silicon substrate 1. Etching is performed with a resist mask 4 as a mask. At this time, the surface region of the substrate 1 is exposed from a boundary line, which is separated from an intended boundary line X between an N-type well layer and a P-type well layer, by a specified distance (d). N-type impurity ions are implanted, and an N-type ion implanted layer 5 is formed. When heat treatment is performed, the N-type impurities, which are implanted into the substrate 1, are diffused in the lateral direction, and an N-type well layer 51 is formed. P-type impurity ions are implanted, and a P-type ion implanted layer 7 is formed. When heat treatment is performed, the P-type impurities, which are implanted into the substrate 1, are diffused in the lateral direction, and a P-type well layer 71 is formed.

10. 发明专利

JPS648642A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS648642A
公开(公告)日：1989-01-12
申请号：JP16434987
申请日：1987-06-30
申请人： MITSUBISHI ELECTRIC CORP
发明人： OGAWA TOSHIAKI , OGAWA IKUO , SHIBANO TERUO , NAGATOMO MASAO , OKUMURA YOSHIKI , KATAYAMA TOSHIHARU , ONO YOSHIKAZU , MORITA HIROYUKI
IPC分类号： H01L27/10 , H01L21/76 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PURPOSE:To avoid the deterioration of device characteristics by connecting a first conductor layer like a cell plate formed through a first insulating film in a groove and on a periphery formed on a substrate to a second conductor layer buried by flattening to the surface of the substrate through a second insulating film in the groove by a third conductor layer made of an electrode material, such as polycrystalline silicon or the like. CONSTITUTION:A groove 2 is formed by anisotropically etching on a semiconductor substrate 1, an oxide film 6 is formed by a CVD method or a heat treating method or the like, a cell plate 7 is formed, for example, by a CVD method, an oxide film 9 is then formed by a CVD method or the like, a polycrystalline silicon is formed by a CVD method as a second diffused layer 5 for burying, then flattened by etching back using anisotropically etching, the film 4 is removed by anisotropically or isotropically etching, an electrode material 10 is then deposited by a CVD method or the like, patterned by a photocomposing step, and a gate insulating film, gate electrode wirings are then deposited by a CVD method or the like.

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