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1. 发明专利

JPH1050825A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH1050825A
公开(公告)日：1998-02-20
申请号：JP20003796
申请日：1996-07-30
申请人： MITSUBISHI ELECTRIC CORP
发明人： WAKAMIYA WATARU
IPC分类号： H01L21/768
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and method which can realize a high integration by eliminating the need for providing a dimensional margin for patterning. SOLUTION: First wiring parts 8a and 8c horizontally extended on an interlayer insulating film and second wiring parts 8b and 8d buried into contact holes are formed so that corresponding side faces of the first and second wiring parts are mutually continuous in the same plane. Such a structure is self- alignedly formed by patterning the laminate with use of a first resist film having a groove-shaped opening pattern and a second resist layer having an opening pattern including in its opening region a predetermined region of the groove- shaped opening pattern as masks.

2. 发明专利

JPH1027884A MANUFACTURE OF SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH1027884A
公开(公告)日：1998-01-27
申请号：JP8790897
申请日：1997-04-07
申请人： MITSUBISHI ELECTRIC CORP
发明人： WAKAMIYA WATARU , SATO SHINICHI , OZAKI KOJI , SAKAEMORI TAKAHISA , TANAKA YOSHINORI
IPC分类号： H01L27/108 , H01L21/8242
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method which is capable of enhancing the integration of a memory cell array. SOLUTION: A field shielding electrode layer 13 is formed in an element isolating region on the surface of a semiconductor substrate through the intermediary of a first oxide film 12, surrounding a separate active region. After the field shielding electrode layer 13 is covered with an insulating film, the word line 8 of a transfer gate transistor is formed through the intermediary of a second insulating film. The word line is made to extend over the field shielding electrode in the element isolating region.

3. 发明专利

JPH03173469A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH03173469A
公开(公告)日：1991-07-26
申请号：JP31375689
申请日：1989-12-01
申请人： MITSUBISHI ELECTRIC CORP
发明人： WAKAMIYA WATARU
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To secure a sufficient capacitance even when the area of an element forming region is reduced, by forming, on a lower electrode, a protruding part almost vertical to a substrate, and using the side surfaces of the protruding part as a capacitor. CONSTITUTION:An aperture part 31 whose section is rectangular is formed on an insulating film 30 deposited on an element region. After a conducting film 32 is deposited on the whole surface, the film 32 on the film 30 is selectively eliminated, and the conducting film 32 is left only on the side walls of the aperture part 31. The film 30 is eliminated, and the lower electrode 33 of a capacitor is formed by using the conducting films 29 and 32. As the result of elimination of the film 30, a square cylinder type protruding part 33' almost vertical to a substrate 19 is formed on the electrode 33. After a nitride film is formed on the whole surface, heat treatment is performed in an oxygen atmosphere. Thereby a part of the nitride film is oxidized, and a dielectic film 34 of a capacitor is formed. By depositing a capacitor upper electrode 35 composed of a conducting film on the whole surface, a capacitor C is formed. By depositing an interlayer insulating film 36, a W film 37 and a bit line 38 are formed.

4. 发明专利

JPH0372672A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0372672A
公开(公告)日：1991-03-27
申请号：JP23218689
申请日：1989-09-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： WAKAMIYA WATARU , YONEDA MASAHIRO , OZAKI KOJI , TANAKA YOSHINORI , KIMURA HIROSHI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To secure sufficient capacitance even when memory size is decreased, by forming a first electrode, a second electrode, and a dielectric layer, which constitute a signal charge storing capacitor element, in the manner in which the positions of the end surfaces are aligned. CONSTITUTION:A capacitor 17 is formed by stacking a laminated film of a silicon nitride film and an oxide film, or a dielectric layer 11 composed of dielectric material like a tantalum oxide film, between a first electrode 10 composed of conducting material like polycrystalline silicon and a second electrode 12. A part of the electrode 10 is connected with one side impurity regions 6b, 9b of an access transistor 16. One end-portion of the first electrode 10 stretches on the upper part of a gate electrode 4a via an insulating film 8. The other end-portion passes the upper part of a word line 4b via the insulating film 8, and is positioned on the upper surface of an element isolation region 2. The first electrode 10, the dielectric layer 11, and the second electrode 12 are formed in the manner in which the positions of the end surfaces are aligned on the upper part of the gate electrode 4a.

5. 发明专利

JPH02191340A FIELD EFFECT SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH02191340A
公开(公告)日：1990-07-27
申请号：JP5661189
申请日：1989-03-08
申请人： MITSUBISHI ELECTRIC CORP
发明人： SATO SHINICHI , WAKAMIYA WATARU , SAKAEMORI TAKAHISA , OZAKI KOJI , TANAKA YOSHINORI
IPC分类号： H01L21/265 , H01L21/336 , H01L29/423 , H01L29/78
摘要： PURPOSE:To obtain a field effect semiconductor device which is free from the influence of hot electrons trapped by a side wall insulating film and has excellent characteristics such as a mutual conductance by a method wherein both low impurity concentration diffused layers and high impurity concentration diffused layers are extended to the part under the side part of a gate electrode. CONSTITUTION:An LDD-MOS transistor includes a pair of low impurity concentration n-type diffused layers 5a and 5b formed in the main surface of a semiconductor substrate 1 and a pair of high impurity concentration n-type diffused layers 6a and 6b. In this transistor, as both the n-type diffused layers 5b and 6b of which a drain is composed are extended to the part under the side part of a lower electrode 22 of which a gate electrode 2 is composed, even if the impurity concentration of the low impurity concentration n-type diffused layer 5b is effectively lowered by trapping of produced hot electrons by a side wall insulating film 4 and a gate insulating film 3, the gate electrode 2 can overlap the drain with the high impurity concentration n-type diffused layer 6b. Therefore, the increase of a source resistance, deterioration of a mutual conductance, etc., which are caused by the effective reduction of the concentration of the low impurity concentration n-type diffused layer can be obtained.

6. 发明专利

JPH0294472A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0294472A
公开(公告)日：1990-04-05
申请号：JP24767088
申请日：1988-09-29
申请人： MITSUBISHI ELECTRIC CORP
发明人： OZAKI KOJI , SAKAEMORI TAKAHISA , TANAKA YOSHINORI , WAKAMIYA WATARU , SATO SHINICHI
IPC分类号： H01L21/3205 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/417
摘要： PURPOSE:To lower the resistance of wirings while flattening the wirings by a method wherein the third conductor layers to be formed on impurity regions are formed to be selectively buried in the positions between the first conductivity type layer and the second conductivity type layers. CONSTITUTION:An N channel type MOS transistor is composed of transfer gates 4 and N type impurity diffused regions 60a, 60b to be source/drain regions. Next, tungsten buried layers 19a, 19b are buried in the exposed positions of a substrate 1 to be filled therein between the transfer gates 4 and isolating gates 16 on the surfaces of the N type impurity diffused regions 60a, 60b thereby flattening the whole surface. Furthermore, the tungsten buried layers 19a, 19b are formed to be electrically connected at the small contact gate intervals on the surface of the N type impurity diffused regions 60a, 60b so that the resistance of wirings to the source/drain region may be lowered.

7. 发明专利

JPS641232A METHOD OF MEASURING PATTERN OVERLAY ACCURACY 失效
公开(公告)号：JPS641232A
公开(公告)日：1989-01-05
申请号：JP15729587
申请日：1987-06-23
申请人： MITSUBISHI ELECTRIC CORP
发明人： WAKAMIYA WATARU
IPC分类号： G01N21/88 , G01N21/956 , G03F9/00 , H01L21/027 , H01L21/66
摘要： PURPOSE:To prevent an error by forming a first alignment mark in first step, then covering the top with a film which transmits an irradiated beam used at the time of alignment, and flattening the top of the film. CONSTITUTION:An alignment mark 2a formed in a recess shape in first step on a semiconductor substrate 1 is covered with a thin film 6 of a material which transmits an alignment light, and the film is so selected that the upper face becomes flat in response to a mark step. Then, an alignment mark 5 is formed on a resist film 5 formed in second step. The marks 2a, 5 are scanned by a laser light, scattered light from the step of the mark is detected to accurately measure the overlay deviation.

8. 发明专利

JPS6297326A PROJECTION EXPOSURE DEVICE 失效
公开(公告)号：JPS6297326A
公开(公告)日：1987-05-06
申请号：JP23704285
申请日：1985-10-23
申请人： MITSUBISHI ELECTRIC CORP
发明人： FUJIWARA KEIJI , WAKAMIYA WATARU , NISHIOKA KYUSAKU , OGAWA TOSHIAKI
IPC分类号： G01N21/88 , G01N21/956 , G03F1/00 , G03F1/84 , G03F7/20 , H01L21/027 , H01L21/66
摘要： PURPOSE:To make it possible to effect the inspection in a state that a mask is transported onto a projection lens and to shorten the inspection time as compared with the method that the defect inspection is performed by the exposure and development on a wafer, by providing a sensor for the inspection of a projected image of a mask on an X-Y stage. CONSTITUTION:An X-Y stage 1 movable in X-Y direction is arranged on the plane which a pattern of a mask 4 is projected through a lens by irradiating it with light and a sensor 2 is attached to the surface of the X-Y stage 1. The pattern of the mask 4 illuminated by an illuminating optical system 5 is projected on the X-Y stage 1 by a projection optical system 3. This projected mask 4 image is scanned by two sensors 2 by moving the X-Y stage 1 in X-Y direction and the defect inspection due to a comparison inspection or data reference can be performed.

9. 发明专利

JPS6292959A EXPOSING DEVICE 失效
公开(公告)号：JPS6292959A
公开(公告)日：1987-04-28
申请号：JP23379385
申请日：1985-10-18
申请人： MITSUBISHI ELECTRIC CORP
发明人： OGAWA TOSHIAKI , WAKAMIYA WATARU , NISHIOKA KYUSAKU , FUJIWARA KEIJI
IPC分类号： H01L21/30 , G03F7/20 , H01L21/027
摘要： PURPOSE:To prevent the occurrence of defects due to dust, which is caused when a light shielding plate is moved, and to prevent penumbra blur by providing the light shielding plate, which intercepts the light of a part other than the desired part of a required pattern, under a mask. CONSTITUTION:A masking aperture (light shielding plate) 2 which shields an unnecessary part other than the required pattern of a mask 1 from light is provided under the mask 1. Thus, not only the masking aperture 2 is easily moved even after setting the mask but also the problem of the occurrence of defects due to dust or the like caused by movement is solved. The influence of a penumbra due to the masking aperture 2 is minimized to prevent the penumbra blur.

10. 发明专利

JPS59155933A Forming method of minute pattern 失效
标题翻译：分形式的形成方法
公开(公告)号：JPS59155933A
公开(公告)日：1984-09-05
申请号：JP3121783
申请日：1983-02-25
申请人： Mitsubishi Electric Corp
发明人： MIYAKE KUNIAKI , HATANAKA MASAHIRO , NISHIOKA KIYUUSAKU , WAKAMIYA WATARU , NAKAJIMA MASAYUKI , TAKAYAMA KENJI
IPC分类号： H01L21/027 , G03F7/095 , G03F7/20 , G03F7/26 , G03F7/38 , G03F7/40
CPC分类号： G03F7/40
摘要： PURPOSE:To obtain a resin mask of a minute pattern by laminating and applying first and second photosensitive resins on a material to be etched, exposing and developing and treating the second resin to bore a predetermined opening section, burying the opening section with an organic silicon compound and thermally treating the opening section at a low temperature and removing the first and second resins through etching while using the opening section as a mask. CONSTITUTION:A first photosensitive resin 2 is applied onto a material 1 to be etched, and a second photosensitive resin 3 in approximately 3,000Angstrom thickness thin in an extent that a predetermined pattern size is obtained is applied onto the resin 2. The resin 3 is exposed and developed and treated to bore prescribed opening sections, the opening sections are buried with an organic silicon compound 4, and the compound is cured through heat treatment at a low temperature. Minute patterns consisting of the compounds 4 and the resins 2 under the compounds are acquired through anisotropic etching by O2 plasma while using the compounds 4 as masks, and the material 1 is etched while employing the patterns as masks.
摘要翻译：目的：为了通过将第一和第二感光树脂层压并施加到待蚀刻的材料上来获得微小的图案的树脂掩模，曝光和显影处理第二树脂以穿孔预定的开口部分，将开口部分用有机硅复合并在低温下热处理开口部分，并且在使用开口部分作为掩模的同时通过蚀刻去除第一和第二树脂。构成：将第一感光性树脂2施加到要蚀刻的材料1上，并且将获得预定图案尺寸的程度较薄的约3,000A厚度的第二感光性树脂3施加到树脂2上。树脂3是曝光和显影处理以钻孔规定的开口部分，开口部分用有机硅化合物4掩埋，并且化合物通过在低温下的热处理而固化。由化合物4和化合物2下的树脂2组成的微小图案通过O 2等离子体的各向异性蚀刻而获得，同时使用化合物4作为掩模，并且在使用图案作为掩模的同时蚀刻材料1。

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