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1. 发明专利

JP2000058783A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000058783A
公开(公告)日：2000-02-25
申请号：JP22296398
申请日：1998-08-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKUMURA YOSHIKI
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To prevent increase in a contact resistance between a plug and semiconductor layer for reduced manufacturing cost by, at least, providing a barrier metal layer formed on an inter-layer insulating film and a polysilicon layer which is formed over it and comprises a conductive impurity, and allowing a buried layer to directly connect to the polysilicon layer. SOLUTION: A polysilicon layer 43 comprising an N-type impurity is formed over the entire surface of a barrier metal layer 42, while it is buried in a bit line contact hole 12 a memory cell part and a bit line contact hole 27 at a peripheral circuit part as well to form buried layers 43A and 43B. Thus, no CMP process required for burying a polysilicon plug in the bit line contact holes 12 and 27 is required for reduced manufacturing cost. With a silicide film 41 formed at the upper end of a polysilicon plug 29, a contact resistance is less compared to a case where the barrier metal layer 42 such as TiN or WN directly contacts the polysilicon plug 29.

2. 发明专利

JP2518359B2 失效
公开(公告)号：JP2518359B2
公开(公告)日：1996-07-24
申请号：JP22920788
申请日：1988-09-13
申请人： MITSUBISHI ELECTRIC CORP
发明人： OGAWA IKUO , NAGATOMO MASAO , MATSUKAWA TAKAYUKI , OKUMURA YOSHIKI , MOTOSHIRO HIDEKI , HACHISUGA ATSUSHI
IPC分类号： H01L29/78 , H01L21/265 , H01L21/266 , H01L21/336 , H01L21/8242 , H01L27/10 , H01L27/108

3. 发明专利

JPH0620108B2 失效
公开(公告)号：JPH0620108B2
公开(公告)日：1994-03-16
申请号：JP6943187
申请日：1987-03-23
申请人： MITSUBISHI ELECTRIC CORP
发明人： ISHII TATSUYA , OKUMURA YOSHIKI , NAGATOMO MASAO
IPC分类号： H01L27/04 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108

4. 发明专利

JPH0555163A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0555163A
公开(公告)日：1993-03-05
申请号：JP21819291
申请日：1991-08-29
申请人： MITSUBISHI ELECTRIC CORP
发明人： HACHISUGA ATSUSHI , OKUMURA YOSHIKI
IPC分类号： H01L21/28
摘要： PURPOSE:To reduce and stabilize the contact resistance without a high temperature treatment. CONSTITUTION:A diffused layer 4 and a diffused region 8 are selectively formed on the surface of a semiconductor substrate 1. Then polysilicon 10 is deposited. Silicon ions are implanted 22 in a boundary between the polysilicon 10 and the region 8 (or the layer 4). Further, ions of a conductivity type opposite to that of the substrate 1 are implanted in the entire surface of the polysilicon 10. Accordingly, the silicon ions breaks a boundary oxide film generated when the polysilicon 10 is deposited.

5. 发明专利

JPH04212453A SEMICONDUCTOR STORAGE DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH04212453A
公开(公告)日：1992-08-04
申请号：JP5209791
申请日：1991-03-18
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKUMURA YOSHIKI , ARIMA HIDEAKI , OKUDAIRA TOMOHITO
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/02 , H01L27/105 , H01L27/108
摘要： PURPOSE:To obtain a semiconductor storage device having a well structure which prevents undershoot occurring by an input signal and deterioration of transistor characteristics. CONSTITUTION:A plurality of N well regions and P well regions are formed on the main surface of a semiconductor substrate. The periphery of the P well region is surrounded by the N well region kept at a positive potential. Said N well region forms a junction between a P-type semiconductor substrate and the P well region. Said junction prevents electrons from being injected toward the P well region which electrons are generated from the P-type semiconductor substrate by shoot.

6. 发明专利

JPH0434968A COMPLEMENTARY FIELD-EFFECT TRANSISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0434968A
公开(公告)日：1992-02-05
申请号：JP14219490
申请日：1990-05-30
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKUMURA YOSHIKI
IPC分类号： H01L21/8238 , H01L27/092
摘要： PURPOSE:To assure the reliability and the high speed operation of an N channel MOSFET while avoiding the punch-through in a P channel MOSFET by a method wherein the length in the channel length direction beneath a gate electrode on the surface part of a relatively low concentration impurity region formed so as to extend to the part beneath the gate electrode of an N channel MOSFET is specified to be 0.1mum. CONSTITUTION:An impurity region in relatively low concentration creeping beneath the first gate electrode is formed on both sides of the main surface of the first gate electrode by ion-implantation in the oblique direction using the first gate electrode as a mask. Next, a sidewall spacer in width exceeding 0.2mum in the same direction as the channel length direction is formed on both sidewalls of the first and second gate electrodes. Next, another impurity region in higher concentration ranging with the low concentration impurity region is formed on the main surface of a semiconductor substrate by ion-implantation using the sidewall spacer on both sidewalls of the first gate electrode as a mask. Furthermore, the other P type impurity region is formed on the main surface on both sides of the second gate electrode by ion-implantation using the sidewall spacer on both sidewalls of the second gate electrode as a mask.

7. 发明专利

JPH03263330A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03263330A
公开(公告)日：1991-11-22
申请号：JP6367190
申请日：1990-03-13
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKUMURA YOSHIKI , HACHISUGA ATSUSHI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L23/485 , H01L27/108
摘要： PURPOSE:To easily form a contact part even when the interval between gate electrodes is small, by forming a first conducting layer, via a second insulating film, on the side wall part and the upper part of the gate electrode and forming at least the end portion of a second conducting layer, via a third insulating film, on the first conducting layer. CONSTITUTION:Gate electrodes 3a, 3b, 3c are formed, via a first insulating film 14, on element isolation regions 2a, 2b and between impurity regions 5a, 7a and impurity regions 5b, 7b on a semiconductor substrate 1. A first conducting layer 8c is connected with the one side impurity regions 5a, 7a of a second conductivity type formed between the element isolation regions 2a, 2b on a semiconductor substrate 1 of a first conductivity type, and formed, via second insulating films 6a, 6b, 4a, 4b, on the side wall part and the upper part of the gate electrodes 3a, 3b. A second conduction layer 11 is connected with the other side impurity regions 5a, 7b, and the end portion of the layer 11 is formed on the first conducting layer 8c, via third insulating films 9, 10b. A second wiring layer 13b is connected with the second conducting layer 11.

8. 发明专利

JPH02209765A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02209765A
公开(公告)日：1990-08-21
申请号：JP3060489
申请日：1989-02-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： MOTONAMI KAORU , OKUMURA YOSHIKI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To connect a plurality of capacitors in parallel by providing a field effect transistor, the capacitors, and data wirings electrically coupled to an impurity diffused region. CONSTITUTION:A plurality of impurity diffused regions 103a, 103b having conductivity are formed at a predetermined interval on a surface region partitioned by an interelement isolating oxide film 102, and a polycrystalline silicon gate electrode 105 is formed on a semiconductor substrate 101 between the regions 103a and 103b through a gate oxide film 104 to constitute a FET T. Polycrystalline silicon capacitor electrodes 107a, 107b are formed on the substrate 101 to be electrically coupled to the region 103a, capacitor insulating films 106a-106c and a second polycrystalline silicon capacitor electrode 108 are formed on the electrode to constitute capacitors Ca-Cc. Further, the FET T and FET T are operated according to the states of the signal of data wiring 112 and the signal of the electrode 105 to store charge to become information in the capacitors C-C.

9. 发明专利

JPH0279461A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0279461A
公开(公告)日：1990-03-20
申请号：JP23081888
申请日：1988-09-14
申请人： MITSUBISHI ELECTRIC CORP
发明人： HACHISUGA ATSUSHI , NAGATOMO MASAO , OGAWA IKUO , GENJIYOU HIDEKI , OKUMURA YOSHIKI , MATSUKAWA TAKAYUKI
IPC分类号： H01L21/316 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To prevent generation of notching in a polycrystalline silicon film in the process of removing silicon oxide film selectively with the same mask by forming polycrystal silicon film on the main surface of a semiconductor base board while a silicon oxide film on this polycrystalline silicon film, and providing the silicon oxide film with specified residual stress. CONSTITUTION:After an insulative film 17a consisting of an oxide film is formed on a P-type silicon base board 1, a polysilicon film 15 is deposited over the whole surface, and further thereon a silicon oxide film 18a of superstratum insulation film is deposited in certain conditions. The residual stress in this silicon oxide film 18a (TEOS film) is below 5X10 dyn/cm after film forming. Then a resist film 14 is formed on the silicon oxide film 18a, and this and polysilicon film 15 are simultaneously removed selectively by dry etching using this resist film 14 as a mask. At this time, the silicon oxide film 18a on the polysilicon film 15 has a residual stress below 10 dyn/cm , so that this etching process forms a word line 20 as a gate electrode where no notching will occur.

10. 发明专利

JPS6437852A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6437852A
公开(公告)日：1989-02-08
申请号：JP19486287
申请日：1987-08-04
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKUMURA YOSHIKI
IPC分类号： H01L21/768 , H01L21/31 , H01L23/522
摘要： PURPOSE:To manufacture a semiconductor device simultaneously satisfying the film thickness controllability and tapering of an inter-lay er insulating film by depositing a polysilicon material film as a gate uppermost layer and an intermediate layer in inter-multilayer insulating films and changing these films into silicon oxide films through heat treatment. CONSTITUTION:An LDD-structure transistor TR is formed, and an oxide film 7, a thin polysilicon material film 8 and an oxide film 9 as inter-layer insulating films are deposited in succession. A resist 13 is patterned through photoengraving, the film 8 is employ ed as a monitor for detecting an end point as important point of etching, and the oxide film is etched in an isotropic manner. The film 8 is oxidized completely, and changed into an Si oxide film 8a. The film thickness controllability and tapering of the inter-layer insulating film 9, etc., can be satisfied simultaneously through heat treatment. Polysilicon 11 is deposited, a high melting-point metallic silicide 12 is deposited, and a semiconductor substrate 1 and polysilicon 11 and the metallic silicide 12 are connected. An upper layer wiring for a transfer gate having the two layer structure of the metallic silicide 12 and poly-Si is executed through replication and machining.

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