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1. 发明专利

JP2002271176A VOLTAGE-CONTROLLED OSCILLATOR CIRCUIT 失效
公开(公告)号：JP2002271176A
公开(公告)日：2002-09-20
申请号：JP2001062420
申请日：2001-03-06
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SAKURA YUJI
IPC分类号： H03K3/354 , H03K3/03
摘要： PROBLEM TO BE SOLVED: To suppress the effect of temperature variation or variation in the characteristics of elements constituting a circuit on the oscillation frequency. SOLUTION: When a logic signal C1 is 'H' and a logic signal C2 is 'L', a switching circuit gas to a conducting state and a switching circuit 21 gees to a non-conducting state. Since the potential at the output of an operational amplifier 31 has been applied to the gate of a PMOS transistor 16, its drain current Ic1 is fed to the drain of an NMOS transistor 35. Since the gate of a PMOS transistor 26 has been pulled up to the power supply, a drain current Ic2 is cut off. Since a current (Ids1+Ic1) flows between the source and drain of the NMOS transistor 35, a current (Iref1+Ic1) is fed to a ring oscillator circuit 50. Oscillation frequency is altered by varying a current being fed to the ring oscillator circuit 50, depending on the logic signals C1 and C2.

2. 发明专利

JPH0535362A TIMER COUNTER CIRCUIT 失效
公开(公告)号：JPH0535362A
公开(公告)日：1993-02-12
申请号：JP19161191
申请日：1991-07-31
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SAKURA YUJI , HAMAGUCHI TOSHIFUMI
IPC分类号： G06F1/14 , G06F15/78
摘要： PURPOSE:To minimize logic on an integrated circuit. CONSTITUTION:While using a counter 1 to increase or decrease the value one by one in the case of inputting a cyclic clock 100 and an outside signal detection circuit 3 to detect the input change of an external terminal, the read register of the value of the counter is used as well as a save register to save the value of the counter with the input change of the outside terminal. Thus, the read function of the counter and a function to save the value of the counter with the change at the input signal of the outside terminal can be separately used, and the logic on the integrated circuit is minimized.

3. 发明专利

JP2007288562A Video signal processor 审中-公开
标题翻译：视频信号处理器
公开(公告)号：JP2007288562A
公开(公告)日：2007-11-01
申请号：JP2006114196
申请日：2006-04-18
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SAKURA YUJI
IPC分类号： H01L27/148 , H04N5/243 , H04N5/335 , H04N5/355 , H04N5/361 , H04N5/369 , H04N5/372 , H04N5/376 , H04N5/378
摘要： PROBLEM TO BE SOLVED: To provide a video signal processor, with which the input range of an AD converter 21 is utilized maximally, even when any image signal can be converted into a video signal.
SOLUTION: The video signal processor is constituted of an imaging device 11; a correlation double sampler (CDS) 12, which removes noise components of an imaging signal CCDOUT output from the imaging device 11; an amplifier 15 which amplifies its output signal CDSOUT; a DC voltage generator 52 which provides a DC voltage level of the output signal of the amplifier by a clamp pulse from an OB clamp pulse generating circuit 18; a clamp circuit 19 which clamps the input signal CDSOUT of the amplifier 15 at the DC voltage level, from the DC voltage generation circuit 52; a timing generator (TG) 13, which generates a sampling pulse in the correlation double sampler (CDS) 12; a synchronizing signal generator (SSG) 17 which supplies a synchronizing signal that serves a reference to the timing generator (TG) 13; a drive circuit 14 which drives the image pickup device 11 and a signal processing circuit 20, which converts the imaging signal into the video signal.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：即使当任何图像信号可以被转换为视频信号时，提供一种视频信号处理器，最大限度地利用AD转换器21的输入范围。视频信号处理器由成像装置11构成; 相关双采样器（CDS）12，其去除从成像装置11输出的成像信号CCDOUT的噪声分量; 放大器15，其放大其输出信号CDSOUT; 直流电压发生器52，其通过来自OB钳位脉冲发生电路18的钳位脉冲提供放大器的输出信号的直流电压电平; 钳位电路19，其从直流电压产生电路52将放大器15的输入信号CDSOUT以直流电压电平钳位; 定时发生器（TG）13，其在相关双重采样器（CDS）12中产生采样脉冲; 同步信号发生器（SSG）17，其提供用于参考定时发生器（TG）13的同步信号; 驱动图像拾取装置11的驱动电路14和将成像信号转换为视频信号的信号处理电路20。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2003198368A A/D CONVERTER, A/D CONVERTING METHOD, AND SIGNAL PROCESSOR 审中-公开
公开(公告)号：JP2003198368A
公开(公告)日：2003-07-11
申请号：JP2001393582
申请日：2001-12-26
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NAKA JUNICHI , NOMAZAKI DAISUKE , IKOMA HEIJI , SAKURA YUJI , OKA KOJI , OKAMOTO YOICHI , INAGAKI ZENSHI
IPC分类号： H03M1/00 , H03M1/12
摘要： PROBLEM TO BE SOLVED: To reduce total powder consumption of a system when the performance of an A/D converter required by the system is varied. SOLUTION: The A/D converter 1a varies the resolution by altering a current flowing through an amplifier by an external control signal 4 designating the resolution. COPYRIGHT: (C)2003,JPO

5. 发明专利

JP2003309180A Method of creating capacity 审中-公开
标题翻译：创造能力的方法
公开(公告)号：JP2003309180A
公开(公告)日：2003-10-31
申请号：JP2002113005
申请日：2002-04-16
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SAKURA YUJI
IPC分类号： H01L21/66 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To create an aimed capacity with high accuracy in single creation by suppressing a variation in the creation.
SOLUTION: In a method of creating a capacity, an inspection (1) is added to the creation flow chart of the capacity as a first means of accomplishing the purpose. Consequently, it becomes possible to grasp whether an aimed capacity is formed or not or to recognize the degree of the occurrence of the variation during the course of creation. As a second means of accomplishing the purpose, a multi-mask is prepared so that a varying range which is several fractions or several tens fractions as narrow as the maximum varying range is corrected by preestimating the varying range of a capacity value, and an aimed capacity value is selected by calculating a value from a value obtained from the first means by means of a storage device (3). Therefore, the capacity value can be corrected.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：通过抑制创作的变化，在单一创作中创造高精度的目标能力。解决方案：在创建容量的方法中，将检查（1）添加到容量的创建流程图中，作为实现目的的第一个方法。因此，能够掌握目标容量是否形成，或者识别创作过程中变化的发生程度。作为实现目的的第二手段，制备多掩模，使得通过预先估计容量值的变化范围来校正与最大变化范围一样窄的几个分数或几十个分数的变化范围，并且目标通过从通过存储装置（3）从第一装置获得的值计算值来选择容量值。因此，能够修正容量值。版权所有（C）2004，JPO

6. 发明专利

JPH11298856A IMAGE RECORDER FOR REPRODUCTION 失效
公开(公告)号：JPH11298856A
公开(公告)日：1999-10-29
申请号：JP10614698
申请日：1998-04-16
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MURATA HISAHARU , KASHIRO TAKAO , YASUE TAKESHI , YANO KATSUHISA , SAKURA YUJI
IPC分类号： H04N5/92 , H04N19/13 , H04N19/146 , H04N19/159 , H04N19/164 , H04N19/177 , H04N19/186 , H04N19/196 , H04N19/423 , H04N19/426 , H04N19/46 , H04N19/50 , H04N19/503 , H04N19/593 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/91 , H04N7/32
摘要： PROBLEM TO BE SOLVED: To allow a device to reproduce digital moving image data in a special reproduction mode such as a fast feeding reproduction mode that are predictively coded in compliance with the MPEG2 or the like and recorded without any further modification. SOLUTION: An in-image coded data detection circuit 1 detects in-image coded data from a received data stream and a memory 3 stores the detected data. A data amount calculation circuit 5 measures an amount of the in-image coded data. A header analysis circuit 6 analyzes header information of the received data. A data coding rate decision circuit 2 obtains a coding rate of the in-image coded data based on the information from the data amount calculation circuit 5 and the header analysis circuit 6 to decide a prescribed data coding rate. A data re-coding circuit 4 applies re-coding to the data in the memory based on the obtained coding rate. According to this re-coding, compressed data are multiplexed with the original data for special reproduction and the multiplexed data are recorded on a prescribed position of a ape.

7. 发明专利

JPH05343986A 失效
公开(公告)号：JPH05343986A
公开(公告)日：1993-12-24
申请号：JP14962292
申请日：1992-06-09
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SAKURA YUJI
IPC分类号： H03K21/10
摘要： PURPOSE:To obtain a counter circuit capable of forming an overflow signal detection circuit with a minimum logic on an integrated circuit even when the number of bits of the counter is increased. CONSTITUTION:This counter circuit consists of a counter 1 and an overflow signal detection circuit 2 comprising 2-input logic circuits 23, 22, 21, 20. The 2-input logic circuit 23 outputs an AND signal with respect to a most significant bit Q4 and a bit Q3 of the counter 1 to the 2-input logic circuit 22. The 2-input logic circuit 22 outputs AND between an output 230 of the pre-stage 2-input logic circuit 23 and the bit Q2 to a post-stage of the 2-input logic circuit 23, and the 2-input logic circuit 21 outputs AND between an output 220 of the pre-stage 2-input logic circuit 22 and the bit Q1 to a post-stage of the 2-input logic circuit 21. The 2-input logic circuit 20 outputs AND between an output 210 of the pre-stage 2-input logic circuit 21 and the least significant bit Q0 as an overflow signal 200.

8. 发明专利

JP2007019861A Analog switching circuit and constant current generation circuit 审中-公开
标题翻译：模拟开关电路和恒流电流发生电路
公开(公告)号：JP2007019861A
公开(公告)日：2007-01-25
申请号：JP2005199148
申请日：2005-07-07
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SAKURA YUJI
IPC分类号： H03K17/14 , H03F3/34 , H03K17/687
摘要： PROBLEM TO BE SOLVED: To suppress the variation of an on resistance value of an analog switching circuit caused by a temperature change. SOLUTION: The analog switching circuit is provided with a switch (11), a first control circuit (12) and a second control circuit (13). In the switch (11), first and second P type transistors (111) and (112) connected in series and first and second N type transistors (113) and (114) connected in series are connected in parallel, and first and second terminals (115) and (116) are provided at both connected ends respectively. In the first control circuit (12), an output voltage is reduced in accordance with an increase in temperature, and the output voltage is supplied to the gate of the second P type transistor (112). In the second control circuit (13), an output voltage is increased in accordance with an increase in temperature, and the output voltage is supplied to the gate of the second N type transistor (114). COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：抑制由温度变化引起的模拟开关电路的导通电阻值的变化。解决方案：模拟开关电路设置有开关（11），第一控制电路（12）和第二控制电路（13）。在开关（11）中，串联连接的第一和第二P型晶体管（111）和（112）并联连接的第一和第二N型晶体管（113）和（114）并联连接，第一和第二端子（115）和（116）分别设置在两个连接端。在第一控制电路（12）中，输出电压根据温度的升高而减小，输出电压被提供给第二P型晶体管（112）的栅极。在第二控制电路（13）中，输出电压根据温度升高而增加，输出电压被提供给第二N型晶体管（114）的栅极。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2003090866A INSPECTION METHOD OF AD CONVERTER 审中-公开
公开(公告)号：JP2003090866A
公开(公告)日：2003-03-28
申请号：JP2001283283
申请日：2001-09-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SAKURA YUJI
IPC分类号： G01R31/316 , G01R31/00 , G01R31/28 , H03M1/10
摘要： PROBLEM TO BE SOLVED: To solve the convention problem in the inspection of an integrated circuit 4 loaded with a digital circuit 3 and an AD converter in combination wherein the digital circuit 3 and the AD converter 2 are independently inspected, so that much time is required for the inspection of the AD converter because it takes long to read the analog input signals 21 of the AD converter from the outside of the integrated circuit 4. SOLUTION: Not the digital circuit 3 and the AD converter 2 are independently inspected, but the digital circuit 3 and the AD converter 2 are inspected with one inspection pattern, whereby the necessity of reading the analog input signal 21 from the outside is dispensed with. Accordingly, the inspection time of the AD converter 2 can be shortened, and the inspection cost can be also reduced.

10. 发明专利

JPH11341439A VIDEO REPRODUCING DEVICE CAPABLE OF GENERATING SYNCHRONIZING REFERENCE SIGNAL FOR SPECIAL REPRODUCTION 失效
公开(公告)号：JPH11341439A
公开(公告)日：1999-12-10
申请号：JP14745098
申请日：1998-05-28
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YASUE TAKESHI , KASHIRO TAKAO , SAKURA YUJI , MURATA HISAHARU
IPC分类号： H04N5/92 , H04N19/00 , H04N19/50 , H04N7/32
摘要： PROBLEM TO BE SOLVED: To allow a digital video device to make special reproduction with correct time display. SOLUTION: The device is provided with a means 2 that reproduces recorded data, a means 3 that selects data in matching with data for special reproduction and usual reproduction as decoded data, a means 4 that eliminates a 1st synchronizing reference signal substantially added to selected special reproduction data from the data, a means 5 that generates a 2nd synchronizing reference signal for special reproduction, a means 6 that adds the 2nd synchronizing reference signal to the data for special reproduction, and a means 7 that decodes the data for special reproduction to which the 2nd synchronizing reference signal is added at special reproduction into data with an original data form. Thus, a special reproduction video image is displayed at a correct time even when no synchronizing reference signal is included in recorded data by eliminating the synchronizing reference signal and newly adding the synchronizing reference signal to data without rewriting the synchronizing reference signal for data for special reproduction. Furthermore, only the reproduction side can conduct correct special reproduction independently of recording of a recording medium.

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