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1. 发明专利

JP2004266034A Semiconductor integrated circuit and method of designing the same 审中-公开
公开(公告)号：JP2004266034A
公开(公告)日：2004-09-24
申请号：JP2003053623
申请日：2003-02-28
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TOMIOKA SHINICHI , TANI MASAHIRO
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/04
摘要： PROBLEM TO BE SOLVED: To solve the problem that, when automatic duty insurance is executed, logical equalization for checking whether logical matching is attained or not before and after modification of a single circuit cannot be insured because a logical changed is made in a single circuit in each layer.
SOLUTION: Duty insurance of clock is performed by calculating a duty ratio of high level and low level periods of clock and sequentially insuring this duty ratio from the layer near the flip-flop in the step 601, providing a first inverter before the CTS in the step 602 at the layer including the flip-flop, providing a second inverter at the area insuring the duty between the input and the first inverter in the step 603, and providing the first inverter before the output in the layer other than the layer including the flip-flop and also providing the second inverter to the area for insuring the duty between the input and output.
COPYRIGHT: (C)2004,JPO&NCIPI

2. 发明专利

JP2003036283A Logical simulation device and its method 审中-公开
标题翻译：逻辑仿真器件及其方法
公开(公告)号：JP2003036283A
公开(公告)日：2003-02-07
申请号：JP2001224132
申请日：2001-07-25
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TOMIOKA SHINICHI , NINOMIYA KAZUKI
IPC分类号： G01R31/28 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a highly-precise logical simulation device and to reduce a verification period in logical simulation by taking into consideration the simulation execution sequence of sequence circuits whose output signal is a clock signal.
SOLUTION: The logical simulation device according to this invention comprises a selection means 2 for selecting from sequence circuits only those sequence circuits whose output is a clock signal, a preceding means 3 for preprocessing logical simulation of the sequence circuits selected by the selection means 2, and a continuation means 4 for executing the logical simulation of other sequence circuit configurations.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供高精度的逻辑模拟装置，并通过考虑其输出信号是时钟信号的序列电路的仿真执行序列来减少逻辑仿真中的验证周期。解决方案：根据本发明的逻辑模拟装置包括一个选择装置2，用于从序列电路中仅选择输出为时钟信号的那些序列电路，用于预处理由选择装置2选择的序列电路的逻辑仿真的先前装置3，以及用于执行其他顺序电路配置的逻辑仿真的延续装置4。

3. 发明专利

JP2006278785A Delay control method and wiring delay control cell library 审中-公开
标题翻译：延迟控制方法和接线延迟控制单元库
公开(公告)号：JP2006278785A
公开(公告)日：2006-10-12
申请号：JP2005096489
申请日：2005-03-29
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TOMIOKA SHINICHI , KUBO TATSURO
IPC分类号： H01L21/82 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a delay control method and delay control cell library in which the step of verifying and determining rounding of a waveform can be obviated and a design time can be shortened.
SOLUTION: In the delay control method, a wiring delay control cell 300 used for controlling delay of a route to control the wiring delay in a semiconductor integrated circuit when designing the semiconductor integrated circuit comprises wiring 321, and a wiring driving semiconductor device 311 which has a driving capability corresponding to wiring resistance and capacitance of the wiring and drives the wiring. The wiring delay caused by wiring resistance and capacitance is controlled using the wiring delay control cell 300, and then the gate delay of the route is controlled by a gate delay control cell comprising only a semiconductor device.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以消除验证和确定波形舍入的步骤的延迟控制方法和延迟控制单元库，并且可以缩短设计时间。解决方案：在延迟控制方法中，当设计半导体集成电路时，用于控制半导体集成电路中的布线延迟的路线的延迟的布线延迟控制单元300包括布线321和布线驱动半导体装置 311具有对应于布线电阻和布线电容的驱动能力并驱动布线。使用布线延迟控制单元300控制由布线电阻和电容引起的布线延迟，然后由仅包括半导体器件的栅极延迟控制单元控制路径的栅极延迟。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2003337844A Method for delay adjustment and method for delay value calculation 有权
标题翻译：延迟调整方法和延迟值计算方法
公开(公告)号：JP2003337844A
公开(公告)日：2003-11-28
申请号：JP2002146468
申请日：2002-05-21
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TOMIOKA SHINICHI , TANI MASAHIRO
IPC分类号： G06F17/50 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To shorten the design period of a semiconductor integrated circuit by reducing layout man-hours required for one more delay adjustment by preventing the fluctuation of the delay adjustment under each semiconductor process condition. SOLUTION: In this method for delay adjustment, a delay value and skew prior to delay adjustment are calculated under each of the plurality of process conditions of a semiconductor integrated circuit on the basis of layout information ( a step ST1). When no circuit operation can be guaranteed with the delay value prior to delay adjustment under the predetermined process condition, a predicted delay value and predicted skew under the predetermined process condition are calculated on the basis of the delay value and skew prior to the delay adjustment under a standard process condition (a step ST3). Then, when the circuit operation can be guaranteed with the predicted delay value under the predetermined process condition, the delay generated in the path is adjusted by using the delay adjusting cell (a step ST6). COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：通过防止在每个半导体工艺条件下的延迟调整的波动，通过减少一个延迟调整所需的布局工时来缩短半导体集成电路的设计周期。解决方案：在这种延迟调整方法中，基于布局信息，在半导体集成电路的多个处理条件的每个处理条件下计算延迟调整之前的延迟值和偏移（步骤ST1）。当在预定的处理条件下在延迟调整之前不能保证具有延迟值的电路操作时，根据在延迟调整之前的延迟值和偏差来计算在预定处理条件下的预测延迟值和预测偏差标准处理条件（步骤ST3）。然后，当在预定处理条件下可以用预测延迟值保证电路操作时，通过使用延迟调整单元来调整在路径中产生的延迟（步骤ST6）。版权所有（C）2004，JPO

5. 发明专利

JP2003303031A Clock control device 有权
标题翻译：时钟控制装置
公开(公告)号：JP2003303031A
公开(公告)日：2003-10-24
申请号：JP2002110324
申请日：2002-04-12
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TOMIOKA SHINICHI , KISHIMOTO YOSHIHIRO , MIKI YOICHIRO , TANI MASAHIRO
IPC分类号： G06F1/06 , G06F1/10 , H01L21/822 , H01L27/04 , H03K17/00
摘要： PROBLEM TO BE SOLVED: To provide a clock control device which prevents the fluctuation of clock and shortens designing time by reducing the number of times of delay adjustment. SOLUTION: The clock control device 100 is provided with a dividing circuits 12a, 12b which divide clocks CK100, CK200; delay adjustment circuits 13a-13f which adjust delay of a clock which are synchronized; selection circuits 14a-14c which select either the clock or a clock of the divided clock; delay adjustment circuits 15a-15d which adjust delay between the clock selected in the selection circuits 14a-14c and a clock branched from the clock; and selection circuits 16a-16c which select and output for each asynchronous 2 systems clock from the output of the delay adjustment circuits 15a-15d, undivided clock among the output of the selection circuits 14a-14c, and CK300. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种通过减少延迟调整次数来防止时钟波动并缩短设计时间的时钟控制装置。时钟控制装置100具有分频电路12a，12b，其将时钟CK100，CK200分频; 延迟调整电路13a-13f，其调整同步的时钟的延迟; 选择电路14a-14c，其选择时钟或分频时钟的时钟; 延迟调整电路15a-15d，其调整在选择电路14a-14c中选择的时钟与从时钟分支的时钟之间的延迟; 以及从延迟调整电路15a-15d的输出中选择并输出每个异步2系统时钟的选择电路16a-16c，选择电路14a-14c和CK300的输出之间的未分频时钟。版权所有（C）2004，JPO

6. 发明专利

JP2007043622A Clock generating apparatus 审中-公开
标题翻译：钟表生成装置
公开(公告)号：JP2007043622A
公开(公告)日：2007-02-15
申请号：JP2005228180
申请日：2005-08-05
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TOMIOKA SHINICHI , KISHIMOTO YOSHIHIRO , KUBO HIRONORI , SEKIGUCHI YUJI
IPC分类号： H03K5/05 , G06F1/08 , H03K5/00
摘要： PROBLEM TO BE SOLVED: To solve the problem that jitter or duty deterioration of N-mutiplied (N is a positive integer) clock may occur by varying a delay value of a delay circuit because of process variation in the prior art where the N-multiplied clock is generated by exclusively ORing N clocks delayed for a 1/2N term by the delay circuit. SOLUTION: According to the present invention, a signal delayed for a 1/2N (N is a positive integer) term in advance is input from the outside, so that delay of a delay circuit is not varied by variation of semiconductor manufacturing processes. Therefore, jitter or duty deterioration can be reduced for an N-multiplied clock generated by exclusive OR, so that a high-precision N-multiplied clock can be generated. Furthermore, the N-multiplied clock is output outside a semiconductor integrated circuit, frequency dispersion or duty deterioration is computed and an input timing and a duty of the input signal are adjusted, thereby supplying a high-precision N-multiplied clock. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题为了解决由于现有技术中的工艺变化而改变延迟电路的延迟值，可能会发生N倍频（N为正整数）时钟的抖动或占空比恶化的问题，其中通过对延迟电路延迟1 / 2N项的N个时钟进行异或运算，产生N倍乘时钟。解决方案：根据本发明，从外部输入预先延迟1 / 2N（N为正整数）项的信号，使得延迟电路的延迟不会因半导体制造的变化而变化流程。因此，通过异或产生的N倍时钟可以降低抖动或占空比恶化，从而可以产生高精度的N倍时钟。此外，将N倍时钟输出到半导体集成电路外部，计算频率色散或占空比劣化，并且调节输入定时和输入信号的占空比，从而提供高精度的N倍时钟。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2007148914A Latch timing adjustment device and adjustment method therefor 审中-公开
标题翻译：锁定时间调整装置及其调整方法
公开(公告)号：JP2007148914A
公开(公告)日：2007-06-14
申请号：JP2005344196
申请日：2005-11-29
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SEKIGUCHI YUJI , MIKI YOICHIRO , KISHIMOTO YOSHIHIRO , TOMIOKA SHINICHI
IPC分类号： G06F12/00
摘要： PROBLEM TO BE SOLVED: To attain a latch timing adjustment device capable of adjusting difference between rising edge timing and trailing edge timing of data input from a memory.
SOLUTION: The latch timing adjustment device has: a data delay part 14A which generates delay data D1 more delayed by an instructed amount than that of input data S10; a data delay part 14B which generates delay data D2 having a delay amount different from that of the delay data D1; an edge adjustment part 15 which performs a logic operation to the delay data D1, D2 to generate delay data D3; a latch circuit 16 which latches the delay data D3 at prescribed timing; a comparison circuit 17 which compares the latched data S16a with an expectation value; a determination part 18 which determines delay amounts which should be set in the data delay parts 14A, 14B based on comparison results and delay control parts 19A, 19B which output delay control signals S19a, S19b for instructing the delay amounts of the data delay parts 14A, 14B.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：获得能够调整从存储器输入的数据的上升沿定时和后沿定时之间的差异的锁存定时调整装置。锁存定时调整装置具有：数据延迟部14A，其生成比输入数据S10更延迟了指示量的延迟数据D1; 产生具有与延迟数据D1不同的延迟量的延迟数据D2的数据延迟部分14B; 边缘调整部15，对延迟数据D1，D2进行逻辑运算，生成延迟数据D3; 锁存电路16，其以规定的定时锁存延迟数据D3; 将锁存数据S16a与期望值进行比较的比较电路17; 确定部分18，其基于比较结果确定在数据延迟部分14A，14B中应该设置的延迟量;以及延迟控制部分19A，19B，延迟控制部分19A，19B输出用于指示数据延迟部分14A的延迟量的延迟控制信号S19a，，14B。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2002323973A INSTRUCTION CODE PROCESSOR AND INSTRUCTION CODE GENERATING METHOD 失效
公开(公告)号：JP2002323973A
公开(公告)日：2002-11-08
申请号：JP2001126313
申请日：2001-04-24
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TOMIOKA SHINICHI , NINOMIYA KAZUKI , SEKI MICHIO
IPC分类号： G06F12/08 , G06F9/30 , G06F9/38
摘要： PROBLEM TO BE SOLVED: To provide an instruction code processor with which processing efficiency is improved by reducing the time required for expanding processing of an instruction code. SOLUTION: An instruction submemory 13 as a storage means of small capacity is provided between an expansion circuit 12 and an arithmetic part 14, instruction codes successively outputted from an instruction memory 11 are expanded by the expansion circuit 12 and stored in the instruction submemory 13 beforehand, and the arithmetic part 14 reads the instruction codes out of the instruction submemory 13.

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