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1. 发明专利

JP2007235524A Variable gain amplifier circuit 审中-公开
标题翻译：可变增益放大器电路
公开(公告)号：JP2007235524A
公开(公告)日：2007-09-13
申请号：JP2006054557
申请日：2006-03-01
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAKAMURA MASANORI , MIYAZAKI TAKAHITO , KOMORI HIROSHI
IPC分类号： H03G1/04 , H03G3/10
摘要： PROBLEM TO BE SOLVED: To provide a variable gain amplifier circuit for which a change in input/output impedance which appears when the gain changes can be corrected.
SOLUTION: In the variable gain amplifier circuit, a function circuit having capacitance function is connected to the input terminal of a transistor 101 for signal amplification. By controlling the function circuit having the variable capacitance function, a change can be corrected in the base-emitter capacitance value of the transistor for signal amplification when the gain changes, resulting in leading to suppression of a change in input/output impedance.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可变增益放大器电路，其可以校正当增益改变时出现的输入/输出阻抗的变化。解决方案：在可变增益放大器电路中，具有电容功能的功能电路连接到用于信号放大的晶体管101的输入端子。通过控制具有可变电容功能的功能电路，当增益改变时，可以在用于信号放大的晶体管的基极 - 发射极电容值中校正改变，导致抑制输入/输出阻抗的变化。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2006101108A Relative variation reduction layout 审中-公开
标题翻译：相对变化减少布局
公开(公告)号：JP2006101108A
公开(公告)日：2006-04-13
申请号：JP2004283876
申请日：2004-09-29
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MIYAWAKI DAISUKE , KOMORI HIROSHI
IPC分类号： H03F3/45
摘要： PROBLEM TO BE SOLVED: To reduce the deviation of two-line output by the relative variation in a semiconductor integrated circuit, such as a differential amplifier circuit, etc.
SOLUTION: The semiconductor integrated circuit constituted by differential transistor pairs, such as the differential amplifier, etc., includes at least one conduction type region, and includes a plurality of bipolar transistors which share the conduction type region as a collector region. The plurality of the bipolar transistors share each base electrode terminal mutually. The plurality of the bipolar transistors share each emitter electrode terminal mutually. The plurality of the bipolar transistors have a layout where each collector electrode terminal is provided independently.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过诸如差分放大器电路等的半导体集成电路的相对变化来减少双线输出的偏差。解决方案：由差分晶体管对构成的半导体集成电路诸如差分放大器等包括至少一个导电类型区域，并且包括共享作为集电极区域的导电类型区域的多个双极晶体管。多个双极晶体管相互共享每个基极端子。多个双极晶体管相互共享每个发射极电极端子。多个双极晶体管具有独立地设置各集电极端子的布局。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006060472A Receiving front end circuit, receiving circuit and communication equipment using the same 审中-公开
标题翻译：接收前端电路，接收电路和使用相同的通信设备
公开(公告)号：JP2006060472A
公开(公告)日：2006-03-02
申请号：JP2004239483
申请日：2004-08-19
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ISHIDA KAORU , KOMORI HIROSHI
IPC分类号： H03D7/14 , H04B1/26
CPC分类号： H04B1/1607 , H03D7/1433 , H03D7/1458 , H03D7/1491 , H03D2200/0025 , H03D2200/0033 , H03D2200/0043
摘要： PROBLEM TO BE SOLVED: To provide a receiving front end circuit of low current consumption in which an IF output level is not remarkably lowered even under an unexpected strong input condition, and a receiving circuit for not generating errors in receiving level detection. SOLUTION: An average level detection circuit 10 detects the level of baseband output signals or the input signals of a mixer circuit. A smoothing circuit 11 removes AC components from the output signals of the average level detection circuit 10. A reference comparator circuit 12 outputs level suppression signals when the output signals of the smoothing circuit 11 exceed a prescribed reference voltage. A limiter circuit 13 suppresses the bias current of the mixer circuit by controlling a bias circuit 14 when the level suppression signals are outputted from the reference comparator circuit 12. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供即使在意外的强输入条件下IF输出电平也不显着降低的低电流消耗的接收前端电路，以及用于不产生接收电平检测中的错误的接收电路。解决方案：平均电平检测电路10检测基带输出信号的电平或混频器电路的输入信号。平滑电路11从平均电平检测电路10的输出信号中除去AC成分。当平滑电路11的输出信号超过规定的基准电压时，基准比较电路12输出电平抑制信号。限幅电路13通过在从基准比较器电路12输出电平抑制信号时控制偏置电路14来抑制混频器电路的偏置电流。（C）2006，JPO＆NCIPI

4. 发明专利

JP2005198084A Differential oscillation circuit 审中-公开
标题翻译：差异振荡电路
公开(公告)号：JP2005198084A
公开(公告)日：2005-07-21
申请号：JP2004003012
申请日：2004-01-08
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KOMORI HIROSHI
IPC分类号： H03B5/12
CPC分类号： H03B5/1215 , H03B5/1228
摘要： PROBLEM TO BE SOLVED: To provide a differential oscillation circuit which is capable of causing a differential oscillator and a differential buffer amplifier to function with a common operating current. SOLUTION: A resonator 14 having a middle point of an inductor 16 as a nodal point is provided, and a differential oscillator 12 to which the operating current is supplied from the middle point of the inductor 16 and a differential buffer amplifier 11 having a pair of bipolar transistors 24 and 25 operated with the operating current as a tail current are provided, and they are so configured that an output signal of the differential oscillator 12 is inputted to the differential buffer amplifier 11. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够使差分振荡器和差分缓冲放大器与公共工作电流一起工作的差分振荡电路。提供具有作为节点的电感器16的中点的谐振器14，以及从电感器16的中点向其提供工作电流的差分振荡器12和具有提供以工作电流作为尾电流工作的一对双极晶体管24和25，并且它们被配置为使得差分振荡器12的输出信号被输入到差分缓冲放大器11.版权所有：（C ）2005年，日本特许厅和NCIPI

5. 发明专利

JP2004048429A Power-on reset circuit 审中-公开
标题翻译：上电复位电路
公开(公告)号：JP2004048429A
公开(公告)日：2004-02-12
申请号：JP2002203811
申请日：2002-07-12
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KOMORI HIROSHI
IPC分类号： H03K17/22
摘要： PROBLEM TO BE SOLVED: To provide a power-on reset circuit capable of being stably operated regardless of the rise speed of a power voltage without needing any steady state current and suitable for a portable apparatus especially needing low power consumption.
SOLUTION: This power-on reset circuit is provided with a charging circuit 1, a CMOS inverter 2 to which the charging voltage of the capacitor of the charging circuit 1 is inputted, a flip flop 4 to be operated with the output signal of the CMOS inverter 2 as a clock, a transistor 5 to be conduction-controlled according to the output signal of the flip flop 4, and a reset pulse generating circuit 6 for generating a reset pulse until a power supply voltage exceeds a predetermined value. When a power is supplied, the voltage of the capacitor of the charging circuit 1 exceeds a predetermined voltage so that steady currents running through the reset pulse generating circuit 6 can be interrupted.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种能够稳定地操作的上电复位电路，无论电源电压的上升速度如何，而不需要任何稳态电流，并且适合于特别需要低功耗的便携式设备。
解决方案：该上电复位电路设置有充电电路1，充电电路1的电容器的充电电压被输入的CMOS反相器2，用于输出信号的触发器4 CMOS反相器2作为时钟，根据触发器4的输出信号进行导通控制的晶体管5以及用于产生复位脉冲直到电源电压超过预定值的复位脉冲发生电路6。当供电时，充电电路1的电容器的电压超过预定电压，从而可以中断通过复位脉冲发生电路6的稳定电流。版权所有（C）2004，JPO

6. 发明专利

JPH05343970A 失效
公开(公告)号：JPH05343970A
公开(公告)日：1993-12-24
申请号：JP15172392
申请日：1992-06-11
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KOMORI HIROSHI
IPC分类号： H03K17/62
摘要： PURPOSE:To decrease crosstalk between output terminals in the signal changeover circuit in which an input signal is switched and outputted to output terminals of 2 systems. CONSTITUTION:This circuit is the signal changeover circuit having an input terminal 16, a switching terminal 17 and output terminals 18, 19 and emitters of transistors(TRs) 20, 21 whose bases connect to ground in terms of AC are respectively connected to the output terminals 18, 19. Then either of the output terminals 18, 19 is to be worked is selected by a setting voltage of the switching terminal 17 and the current is switched so as to supply a current to the TR 20 or 21 connecting to the output terminal 18 or 19 in the inactive state. By the current switching, since the impedance of the inactive output terminal is low, the leakage of a signal via a junction capacitance of the TR is suppressed and crosstalk between the output terminals is reduced.

7. 发明专利

JPH03102508A REFERENCE VOLTAGE GENERATING CIRCUIT 失效
公开(公告)号：JPH03102508A
公开(公告)日：1991-04-26
申请号：JP24123089
申请日：1989-09-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KOMORI HIROSHI , SHIMAZU TAKAYUKI
IPC分类号： G05F3/26 , H03F3/343
摘要： PURPOSE:To realize a satisfactory reference voltage generating circuit to generate a reference voltage, which is strongly affected by an Early effect, by inserting a resistor to the collector of a transistor to output a current. CONSTITUTION:PNP transistors 1 and 2 are composed in current mirror constitution and accordingly, the current in the same size as a constant current source 3 is outputted from the collector of the PNP transistor 2. By the flow of the current to resistors 4 and 7, the reference voltage is generated in a reference voltage terminal 6 and a voltage effect is generated in the resistor 7 as well. As a result, a voltage between the collector and emitter of the PNP transistor 2 is reduced in comparison with a case that there is no resistor 7, and the influence of the Early effect is strongly received. Namely, the rate of the change in the reference voltage, which is generated in the reference voltage terminal 6, is enlarged to the change in a voltage to be impressed to a power supply terminal 5.

8. 发明专利

JPH0372709A VARIABLE IMPEDANCE CIRCUIT 失效
公开(公告)号：JPH0372709A
公开(公告)日：1991-03-27
申请号：JP27743489
申请日：1989-10-24
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MORITA YOICHI , KOMORI HIROSHI , YOKOYAMA AKIO
IPC分类号： H03H11/46 , H03F3/45
摘要： PURPOSE:To realize a variable impedance circuit with two differential amplifying circuits by providing first and second differential amplifying circuits which have impedance elements connected between emitters of a transistor pair. CONSTITUTION:A differential amplifying circuit consists of TRs Q1, Q2 and a capacity element 3 connected between their emitters, and a differential amplifying circuit 2 consists of TRs Q3, Q4 and a resistance element 5 connected between their emitters. A pair of output terminals of the differential amplifying circuit 1 is connected to a pair of input terminals of the differential amplifying circuit 2, and a pair of output terminals of the differential amplifying circuit 2 is connected to a pair of input terminals of the differential amplifying circuit 1. a resistance element 6 is connected between input terminals of the differential amplifying circuit 2. Therefore, a ratio of resistance values of resistance elements 5 and 6 is selected to obtain another capacitance value from the capacitance element 3. Thus, the variable impedance circuit consists of two differential amplifying circuits, and the circuit constitution is simplified.

9. 发明专利

JPH01245315A CONSTANT VOLTAGE CIRCUIT 失效
公开(公告)号：JPH01245315A
公开(公告)日：1989-09-29
申请号：JP7359088
申请日：1988-03-28
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KOMORI HIROSHI , RYU TAKASHI , MASAGAKI TOSHIHIRO
IPC分类号： G05F1/56
摘要： PURPOSE:To reduce the number of elements without using a buffer circuit by converting a reference voltage into a voltage directly determined by a resistance ratio and outputting the converted voltage. CONSTITUTION:Current flowing out from a current source 21 is passed through a transistor 15, flows into a resistor 17, and when the sum of voltage applied between the base and emitter of the transistor 15 and voltage applied to the resistor 17 is equal to the band gap of a used semiconductor, the temperature factor of the sum of the voltages goes zero. The voltage is equal to voltage applied to a resistor 19. Current flowing into a resistor 18 is equal to that flowing into the resistor 19 and the ratio of voltages applied to respective resistors 18, 19 is equal to the ratio of the resistor levels and fixed independently of temperature. Thereby, a fixed voltage can be obtained from an output terminal 23.

10. 发明专利

JP2006203588A Frequency converter 审中-公开
标题翻译：频率转换器
公开(公告)号：JP2006203588A
公开(公告)日：2006-08-03
申请号：JP2005013449
申请日：2005-01-21
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KANEHARA TOMOYUKI , IGARASHI MASATOSHI , KOMORI HIROSHI , WATANABE TAKEAKI , TODA SATOSHI
IPC分类号： H03D7/00 , H03D7/14
摘要： PROBLEM TO BE SOLVED: To provide a frequency converter capable of reducing transmission losses of a high frequency signal in a high frequency semiconductor circuit without increasing a circuit scale and ensuring a wide dynamic range in which conversion efficiency for the high frequency signal rises.
SOLUTION: When the frequency converter is provided with a plurality of frequency converters 100 constituted of a high frequency semiconductor circuit and having different gain characteristics, in each of the frequency converters 100, leakage suppressing functions of leakage suppression circuits 108 and 109 connected to mixers 101 and 102 are operated to suppress leakage of the high frequency signal, which is caused by parasitic capacity occurring in a transistor of the high frequency semiconductor circuit.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种能够降低高频半导体电路中的高频信号的传输损耗的频率转换器，而不增加电路规模，并确保高频信号的转换效率上升的宽动态范围。解决方案：在频率转换器设置有由高频半导体电路构成并具有不同增益特性的多个频率转换器100的情况下，在每个变频器100中，连接了泄漏抑制电路108和109的泄漏抑制功能对混频器101和102进行操作，以便抑制由高频半导体电路的晶体管中发生的寄生电容引起的高频信号的泄漏。版权所有（C）2006，JPO＆NCIPI

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